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5008c67002
Author | SHA1 | Date | |
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5008c67002 | ||
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78e533a61f |
@ -16,7 +16,8 @@ class TinyOp(Enum):
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setReadAddr = 4
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setReadAddr = 4
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writeOp = 5
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writeOp = 5
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writeTableOp = 6
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writeTableOp = 6
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invalidOp = 7
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holdDelayOp = 7
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invalidOp = 8
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class TinyRegAddr(Enum):
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class TinyRegAddr(Enum):
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@ -36,6 +37,9 @@ class TinyRegAddr(Enum):
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kPwmDivAddr = 13
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kPwmDivAddr = 13
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kStateAddr = 14
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kStateAddr = 14
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kErrorCodeAddr = 15
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kErrorCodeAddr = 15
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kMaxAllowTmrAddr = 16
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kDelayCoarseAddr = 17
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kDelayFineAddr = 18
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class TinyConst(Enum):
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class TinyConst(Enum):
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kRdRegSrcId = TinyRegAddr.kRdRegAddrAddr.value # 0
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kRdRegSrcId = TinyRegAddr.kRdRegAddrAddr.value # 0
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@ -184,6 +188,7 @@ class Picadae:
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return self.write_tiny_reg( self._pitch_to_i2c_addr( midi_pitch ), op_code, argL )
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return self.write_tiny_reg( self._pitch_to_i2c_addr( midi_pitch ), op_code, argL )
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def set_read_addr( self, i2c_addr, mem_id, addr ):
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def set_read_addr( self, i2c_addr, mem_id, addr ):
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# mem_id: 0=reg_array 1=vel_table 2=eeprom
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return self.write_tiny_reg(i2c_addr, TinyOp.setReadAddr.value,[ mem_id, addr ])
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return self.write_tiny_reg(i2c_addr, TinyOp.setReadAddr.value,[ mem_id, addr ])
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def read_request( self, i2c_addr, reg_addr, byteOutN ):
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def read_request( self, i2c_addr, reg_addr, byteOutN ):
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@ -246,6 +251,19 @@ class Picadae:
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return self.call_op( midi_pitch, TinyOp.noteOffOp.value,
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return self.call_op( midi_pitch, TinyOp.noteOffOp.value,
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[0] ) # TODO: sending a dummy byte because we can't handle sending a command with no data bytes.
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[0] ) # TODO: sending a dummy byte because we can't handle sending a command with no data bytes.
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def set_hold_delay( self, midi_pitch, pulse_usec ):
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return self.call_op( midi_pitch, TinyOp.holdDelayOp.value, list(self._usec_to_coarse_and_fine(pulse_usec)) )
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def get_hold_delay( self, midi_pitch, time_out_ms=250 ):
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res = self.block_on_picadae_read_reg( midi_pitch, TinyRegAddr.kDelayCoarseAddr.value, byteOutN=2, time_out_ms=time_out_ms )
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if len(res.value) == 2:
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res.value = [ self.prescaler_usec*255*res.value[0] + self.prescaler_usec*res.value[1] ]
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return res
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def set_velocity_map( self, midi_pitch, midi_vel, pulse_usec ):
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def set_velocity_map( self, midi_pitch, midi_vel, pulse_usec ):
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coarse,fine = self._usec_to_coarse_and_fine( pulse_usec )
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coarse,fine = self._usec_to_coarse_and_fine( pulse_usec )
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src = TinyConst.kWrAddrFl.value | TinyConst.kWrTableDstId.value
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src = TinyConst.kWrAddrFl.value | TinyConst.kWrTableDstId.value
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@ -258,7 +276,7 @@ class Picadae:
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def set_pwm_duty( self, midi_pitch, duty_cycle_pct ):
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def set_pwm_duty( self, midi_pitch, duty_cycle_pct ):
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if 0 <= duty_cycle_pct and duty_cycle_pct <= 100:
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if 0 <= duty_cycle_pct and duty_cycle_pct <= 100:
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duty_cycle_pct = 100.0 - duty_cycle_pct
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# duty_cycle_pct = 100.0 - duty_cycle_pct
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return self.call_op( midi_pitch, TinyOp.setPwmOp.value, [ int( duty_cycle_pct * 255.0 /100.0 )])
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return self.call_op( midi_pitch, TinyOp.setPwmOp.value, [ int( duty_cycle_pct * 255.0 /100.0 )])
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else:
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else:
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return Result(msg="Duty cycle (%f) out of range 0-100." % (duty_cycle_pct))
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return Result(msg="Duty cycle (%f) out of range 0-100." % (duty_cycle_pct))
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@ -279,6 +297,15 @@ class Picadae:
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def get_pwm_div( self, midi_pitch, time_out_ms=250 ):
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def get_pwm_div( self, midi_pitch, time_out_ms=250 ):
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return self.block_on_picadae_read_reg( midi_pitch, TinyRegAddr.kPwmDivAddr.value, time_out_ms=time_out_ms )
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return self.block_on_picadae_read_reg( midi_pitch, TinyRegAddr.kPwmDivAddr.value, time_out_ms=time_out_ms )
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def set_pwm_div( self, midi_pitch, div, time_out_ms=250 ):
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res = self.get_pwm_duty( midi_pitch )
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if res:
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duty = res.value[0]
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res = self.get_pwm_freq( midi_pitch )
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if res:
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res = self.call_op( midi_pitch, TinyOp.setPwmOp.value, [ int(duty), int(res.value[0]), int(div) ])
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return res
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def write_table( self, midi_pitch, time_out_ms=250 ):
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def write_table( self, midi_pitch, time_out_ms=250 ):
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# TODO: sending a dummy byte because we can't handle sending a command with no data bytes.
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# TODO: sending a dummy byte because we can't handle sending a command with no data bytes.
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return self.call_op( midi_pitch, TinyOp.writeTableOp.value,[0])
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return self.call_op( midi_pitch, TinyOp.writeTableOp.value,[0])
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@ -13,22 +13,24 @@ class PicadaeShell:
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'q':{ "func":None, "minN":0, "maxN":0, "help":"quit"},
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'q':{ "func":None, "minN":0, "maxN":0, "help":"quit"},
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'?':{ "func":"_help", "minN":0, "maxN":0, "help":"Print usage text."},
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'?':{ "func":"_help", "minN":0, "maxN":0, "help":"Print usage text."},
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'w':{ "func":"_write", "minN":-1, "maxN":-1,"help":"write <i2c_addr> <reg_addr> <data0> ... <dataN>"},
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'w':{ "func":"_write", "minN":-1, "maxN":-1,"help":"write <i2c_addr> <reg_addr> <data0> ... <dataN>"},
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'r':{ "func":"_read", "minN":4, "maxN":4, "help":"read <i2c_addr> <src> <reg_addr> <byteN>"},
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'r':{ "func":"_read", "minN":4, "maxN":4, "help":"read <i2c_addr> <src> <reg_addr> <byteN> src: 0=reg_array 1=vel_table 2=eeprom"},
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'v':{ "func":"note_on_vel", "minN":2, "maxN":2, "help":"note-on <pitch> <vel>"},
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'v':{ "func":"note_on_vel", "minN":2, "maxN":2, "help":"note-on <pitch> <vel>"},
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'u':{ "func":"note_on_us", "minN":2, "maxN":3, "help":"note-on <pitch> <usec> <prescale> (1=1, 2=8, 3=64,(4)=256 16us, 5=1024)"},
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'u':{ "func":"note_on_us", "minN":2, "maxN":3, "help":"note-on <pitch> <usec> <prescale> (1=1, 2=8 .5us, 3=64 4us,(4)=256 16us, 5=1024 64us)"},
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'o':{ "func":"note_off", "minN":1, "maxN":1, "help":"note-off <pitch>"},
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'o':{ "func":"note_off", "minN":1, "maxN":1, "help":"note-off <pitch>"},
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'T':{ "func":"set_vel_map", "minN":3, "maxN":3, "help":"table <pitch> <vel> <usec>"},
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'T':{ "func":"set_vel_map", "minN":3, "maxN":3, "help":"table <pitch> <vel> <usec>"},
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't':{ "func":"get_vel_map", "minN":2, "maxN":2, "help":"table <pitch> <vel>"},
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't':{ "func":"get_vel_map", "minN":2, "maxN":2, "help":"table <pitch> <vel>"},
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'D':{ "func":"set_pwm_duty", "minN":2, "maxN":4, "help":"duty <pitch> <percent> {<hz> {<div>}} " },
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'D':{ "func":"set_pwm_duty", "minN":2, "maxN":4, "help":"duty <pitch> <percent> {<hz> {<div>}} " },
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'd':{ "func":"get_pwm_duty", "minN":1, "maxN":1, "help":"duty <pitch>"},
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'd':{ "func":"get_pwm_duty", "minN":1, "maxN":1, "help":"duty <pitch>"},
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'F':{ "func":"set_pwm_freq", "minN":2, "maxN":2, "help":"freq <pitch> <hz> 254=~123Hz"},
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'H':{ "func":"set_hold_delay", "minN":2, "maxN":2, "help":"hold delay <pitch> <usec>"},
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'f':{ "func":"get_pwm_freq", "minN":1, "maxN":1, "help":"freq <pitch>"},
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'h':{ "func":"get_hold_delay", "minN":1, "maxN":1, "help":"hold delay <pitch>"},
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'I':{ "func":"set_pwm_div", "minN":2, "maxN":2, "help":"div <pitch> <div> div:2=2,3=4,4=8,5=16,6=32,7=64,8=128,9=256,(10)=512 32us, 11=1024,12=2048,13=4096,14=8192,15=16384"},
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'F':{ "func":"set_pwm_freq", "minN":2, "maxN":2, "help":"pwm freq <pitch> <hz> 254=~123Hz"},
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'i':{ "func":"get_pwm_div", "minN":1, "maxN":1, "help":"div <pitch>"},
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'f':{ "func":"get_pwm_freq", "minN":1, "maxN":1, "help":"pwm freq <pitch>"},
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'I':{ "func":"set_pwm_div", "minN":2, "maxN":2, "help":"pwm div <pitch> <div> div:2=2,3=4,4=8,(5)=16 1us,6=32,7=64,8=128,9=256,10=512 32us, 11=1024,12=2048,13=4096,14=8192,15=16384"},
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'i':{ "func":"get_pwm_div", "minN":1, "maxN":1, "help":"pwm div <pitch>"},
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'W':{ "func":"write_table", "minN":1, "maxN":1, "help":"write_table <pitch>"},
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'W':{ "func":"write_table", "minN":1, "maxN":1, "help":"write_table <pitch>"},
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'N':{ "func":"make_note", "minN":3, "maxN":3, "help":"note <pitch> <atkUs> <durMs>"},
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'N':{ "func":"make_note", "minN":3, "maxN":3, "help":"note <pitch> <atkUs> <durMs>"},
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'S':{ "func":"make_seq", "minN":5, "maxN":5, "help":"seq <pitch> <atkUs> <durMs> <deltaUs> <note_count>"},
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'S':{ "func":"make_seq", "minN":5, "maxN":5, "help":"seq <pitch> <atkUs> <durMs> <deltaUs> <note_count>"},
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'L':{ "func":"set_log_level","minN":1, "maxN":1, "help":"log <level> (0-1)."}
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'L':{ "func":"set_log_level", "minN":1, "maxN":1, "help":"log <level> (0-1)."}
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}
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}
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def _help( self, _=None ):
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def _help( self, _=None ):
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@ -40,8 +42,8 @@ class PicadaeShell:
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def _write( self, argL ):
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def _write( self, argL ):
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return self.p.write(argL[0], argL[1], argL[2:])
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return self.p.write(argL[0], argL[1], argL[2:])
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def _read( self, argL ):
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def _read( self, i2c_addr, src_id, reg_addr, byteN ):
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return self.p.block_on_picadae_read(argL[0], argL[1], argL[2], argL[3])
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return self.p.block_on_picadae_read(i2c_addr, src_id, reg_addr, byteN)
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def _syntaxError( self, msg ):
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def _syntaxError( self, msg ):
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print("Syntax Error: " + msg )
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print("Syntax Error: " + msg )
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@ -45,7 +45,8 @@ enum
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kSetReadAddr_Op = 4, // Set a read addr. 6 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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kSetReadAddr_Op = 4, // Set a read addr. 6 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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kWrite_Op = 5, // Set write 7 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
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kWrite_Op = 5, // Set write 7 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
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kWriteTable_Op = 6, // Write table to EEprom 9
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kWriteTable_Op = 6, // Write table to EEprom 9
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kInvalid_Op = 7 //
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kHoldDelay_Op = 7, // Set hold delay {<coarse> {<fine>}}
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kInvalid_Op = 8 //
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};
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};
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@ -72,6 +73,10 @@ enum
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kState_idx = 14, // 1=attk 2=hold
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kState_idx = 14, // 1=attk 2=hold
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kError_Code_idx = 15, // Error Code
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kError_Code_idx = 15, // Error Code
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kMax_Coarse_Tmr_idx = 16, // Max. allowable coarse timer value
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kMax_Coarse_Tmr_idx = 16, // Max. allowable coarse timer value
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kDelay_Coarse_idx = 17, // (17,18)=2000 (0,6)=100
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kDelay_Fine_idx = 18,
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kMax_idx
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kMax_idx
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};
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};
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@ -99,12 +104,16 @@ volatile uint8_t ctl_regs[] =
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4, // 10 (1-5) 4=16us per tick
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4, // 10 (1-5) 4=16us per tick
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127, // 11 (0-255) Pwm Duty cycle
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127, // 11 (0-255) Pwm Duty cycle
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254, // 12 (0-255) Pwm Frequency (123 Hz)
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255, // 12 (0-255) Pwm Frequency (123 Hz)
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10, // 13 (0-15) Pwm clock div
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5, // 13 (0-15) Pwm clock div
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0, // 14 state flags 1=attk 2=hold (read/only)
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0, // 14 state flags 1=attk 2=hold (read/only)
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0, // 15 (0-255) Error bit field
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0, // 15 (0-255) Error bit field
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14, // 16 (0-255) Max allowable coarse timer count
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14, // 16 (0-255) Max allowable coarse timer count
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0, // 17 (0-255) Hold coarse delay
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6 // 18 (0-255) Hold fine delay 0,6=100us 0,124=2000us w/ 16us Tmr0 tick
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};
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};
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// These registers are saved to Eeprom
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// These registers are saved to Eeprom
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@ -208,6 +217,34 @@ volatile uint8_t hold_state = 0; // state=0 hold should not be set, state=1 hol
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#define clear_hold() PORTB &= ~(_BV(HOLD_PIN))
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#define clear_hold() PORTB &= ~(_BV(HOLD_PIN))
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#define set_hold() PORTB |= _BV(HOLD_PIN)
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#define set_hold() PORTB |= _BV(HOLD_PIN)
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void hold_begin()
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{
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hold_state = 1;
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// Reset the PWM counter to to OCR1C (PWM TOP) so that it immediately triggers
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// set_hold() and latches any new value for OCR1B (See: 12.2.2 Timer/Counter1 in PWM Mode)
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// If this is not done and OCR1B was modified the first pulse will have the incorrect length.
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TCNT1 = ctl_regs[kPwm_Freq_idx];
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TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // PWM interupt Enable interrupts
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TCCR1 |= ctl_regs[ kPwm_Div_idx]; // 32us period (512 divider) prescaler
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GTCCR |= _BV(PSR1); // Force the pre-scale to be latched by setting PSR1
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}
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void hold_end()
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{
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clear_hold();
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TIMSK &= ~_BV(OCIE0A); // Clear timer interrupt (shouldn't be necessary but doesn't hurt on during note-off message)
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TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // PWM interupt disable interrupts
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TCCR1 = 0; // Stop the PWM timer by setting the pre-scale to 0
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GTCCR |= _BV(PSR1); // Force the pre-scale to be latched by setting PSR1
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hold_state = 0;
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}
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// Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
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// Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
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void tmr0_reset()
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void tmr0_reset()
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{
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{
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@ -217,6 +254,10 @@ void tmr0_reset()
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clear_hold(); // clear the hold pin
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clear_hold(); // clear the hold pin
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hold_state = 0;
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hold_state = 0;
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tmr0_state = 1;
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OCR0A = 0xff;
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/*
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// if a coarse count exists then go into coarse mode
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// if a coarse count exists then go into coarse mode
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if( ctl_regs[kTmr_Coarse_idx] > 0 )
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if( ctl_regs[kTmr_Coarse_idx] > 0 )
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{
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{
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@ -228,6 +269,7 @@ void tmr0_reset()
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tmr0_state = 2;
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tmr0_state = 2;
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OCR0A = ctl_regs[kTmr_Fine_idx];
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OCR0A = ctl_regs[kTmr_Fine_idx];
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}
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}
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*/
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TCNT0 = 0;
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TCNT0 = 0;
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TIMSK |= _BV(OCIE0A); // enable the timer interrupt
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TIMSK |= _BV(OCIE0A); // enable the timer interrupt
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@ -237,31 +279,49 @@ ISR(TIMER0_COMPA_vect)
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{
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{
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switch( tmr0_state )
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switch( tmr0_state )
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{
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{
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case 0:
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case 0: // timer disabled
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// timer is disabled
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break;
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break;
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case 1:
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case 1: // attack coarse mode
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// coarse mode
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// Note: the '+1' here is necessary to absorb an interrupt which is occurring
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if( ++tmr0_coarse_cur >= ctl_regs[kTmr_Coarse_idx] )
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// for an unknown reason. It must have something to do with resetting the
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// OCIE0A interrupt because it doesn't occur on the hold delay coarse timing.
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if( ++tmr0_coarse_cur >= ctl_regs[kTmr_Coarse_idx]+1 )
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{
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{
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tmr0_state = 2;
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tmr0_state = 2;
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OCR0A = ctl_regs[kTmr_Fine_idx];
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OCR0A = ctl_regs[kTmr_Fine_idx];
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}
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}
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break;
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break;
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case 2:
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case 2: // attack fine mode
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// fine mode
|
|
||||||
|
|
||||||
// This marks the end of a timer period
|
|
||||||
|
|
||||||
clear_attack();
|
clear_attack();
|
||||||
|
|
||||||
TCNT1 = 0; // reset the PWM counter to 0
|
// if a coarse delay count exists then go into coarse mode
|
||||||
hold_state = 1; // enable the hold output
|
if( ctl_regs[kDelay_Coarse_idx] > 0 )
|
||||||
TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // PWM interupt Enable interrupts
|
{
|
||||||
TIMSK &= ~_BV(OCIE0A); // clear timer interrupt
|
tmr0_state = 3;
|
||||||
|
tmr0_coarse_cur = 0;
|
||||||
|
OCR0A = 0xff;
|
||||||
|
}
|
||||||
|
else // otherwise go into fine mode
|
||||||
|
{
|
||||||
|
tmr0_state = 4;
|
||||||
|
OCR0A = ctl_regs[kDelay_Fine_idx];
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3: // coarse hold delay
|
||||||
|
if( ++tmr0_coarse_cur >= ctl_regs[kDelay_Coarse_idx] )
|
||||||
|
{
|
||||||
|
tmr0_state = 4;
|
||||||
|
OCR0A = ctl_regs[kDelay_Fine_idx];
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4: // hold delay end
|
||||||
|
TIMSK &= ~_BV(OCIE0A); // clear timer interrupt
|
||||||
|
tmr0_state = 0;
|
||||||
|
hold_begin();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -270,9 +330,11 @@ ISR(TIMER0_COMPA_vect)
|
|||||||
void tmr0_init()
|
void tmr0_init()
|
||||||
{
|
{
|
||||||
TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
|
TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
|
||||||
|
TCCR0A = 0; // Set the timer control registers to their default value
|
||||||
|
TCCR0B = 0;
|
||||||
TCCR0A |= 0x02; // CTC mode
|
TCCR0A |= 0x02; // CTC mode
|
||||||
TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
|
TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
|
||||||
GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
|
GTCCR |= _BV(PSR0); // Trigger the pre-scaler to be reset to the selected value
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -297,26 +359,23 @@ void pwm1_update()
|
|||||||
// At this point TCNT1 is reset to 0, new OCR1B values are latched from temp. loctaion to OCR1B
|
// At this point TCNT1 is reset to 0, new OCR1B values are latched from temp. loctaion to OCR1B
|
||||||
ISR(TIMER1_OVF_vect)
|
ISR(TIMER1_OVF_vect)
|
||||||
{
|
{
|
||||||
clear_hold();
|
set_hold();
|
||||||
}
|
}
|
||||||
|
|
||||||
// Called when TCNT1 == OCR1B
|
// Called when TCNT1 == OCR1B
|
||||||
ISR(TIMER1_COMPB_vect)
|
ISR(TIMER1_COMPB_vect)
|
||||||
{
|
{
|
||||||
if(hold_state)
|
clear_hold();
|
||||||
set_hold();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void pwm1_init()
|
void pwm1_init()
|
||||||
{
|
{
|
||||||
TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // Disable interrupts
|
|
||||||
|
|
||||||
DDRB |= _BV(HOLD_DIR); // setup PB3 as output
|
DDRB |= _BV(HOLD_DIR); // setup PB3 as output
|
||||||
|
|
||||||
TCCR1 |= ctl_regs[ kPwm_Div_idx]; // 32us period (512 divider) prescaler
|
TCCR1 = 0; // Set the control registers to their default
|
||||||
|
GTCCR = 0;
|
||||||
GTCCR |= _BV(PWM1B); // Enable PWM B and disconnect output pins
|
GTCCR |= _BV(PWM1B); // Enable PWM B and disconnect output pins
|
||||||
GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
|
|
||||||
|
|
||||||
pwm1_update();
|
pwm1_update();
|
||||||
|
|
||||||
@ -462,14 +521,6 @@ void on_receive( uint8_t byteN )
|
|||||||
for(i=0; i<stack_idx && i<3; ++i)
|
for(i=0; i<stack_idx && i<3; ++i)
|
||||||
ctl_regs[ kPwm_Duty_idx + i ] = stack[i];
|
ctl_regs[ kPwm_Duty_idx + i ] = stack[i];
|
||||||
|
|
||||||
// if the PWM prescaler was changed
|
|
||||||
if( i == 3 )
|
|
||||||
{
|
|
||||||
cli();
|
|
||||||
pwm1_init();
|
|
||||||
sei();
|
|
||||||
}
|
|
||||||
|
|
||||||
pwm1_update();
|
pwm1_update();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
@ -496,9 +547,7 @@ void on_receive( uint8_t byteN )
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case kNoteOff_Op:
|
case kNoteOff_Op:
|
||||||
TIMSK &= ~_BV(OCIE0A); // clear timer interrupt (shouldn't be necessary)
|
hold_end();
|
||||||
//TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // PWM interupt disable interrupts
|
|
||||||
hold_state = 0;
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case kSetReadAddr_Op:
|
case kSetReadAddr_Op:
|
||||||
@ -518,6 +567,11 @@ void on_receive( uint8_t byteN )
|
|||||||
case kWriteTable_Op:
|
case kWriteTable_Op:
|
||||||
write_table();
|
write_table();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case kHoldDelay_Op:
|
||||||
|
for(i=0; i<stack_idx && i<2; ++i)
|
||||||
|
ctl_regs[ kDelay_Coarse_idx + i ] = stack[i];
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user