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+//| Copyright: (C) 2018-2020 Kevin Larke <contact AT larke DOT org>
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+//| License: GNU GPL version 3.0 or above. See the accompanying LICENSE file.
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+
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+// w 60 0 1 10 : w i2c_addr SetPWM enable duty_val
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+// w 60 5 12 8 32 : w i2c_addr write addrFl|src coarse_val
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+// w 60 4 0 5 : w i2c_addr read src read_addr (set the read address to register 5)
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+// r 60 4 3 : r i2c_addr <dum> cnt (read the first 3 reg's beginning w/ 5)
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+/*
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+ AT TINY 85
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+ +--\/--+
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+ RESET _| 1 8 |_ +5V
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+ ~OC1B HOLD PINB3 _| 2 7 |_ SCL yellow
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+ OC1B ONSET PINB4 _| 3 6 |_ PINB1 LED
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+ GND _| 4 5 |_ SDA orange
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+ +------+
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+ * = Serial and/or programming pins on Arduino as ISP
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+*/
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+
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+
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+// This program acts as the device (slave) for the control program i2c/a2a/c_ctl
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+#define F_CPU 16000000L
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+
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+#include <stdio.h>
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+#include <avr/io.h>
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+#include <util/delay.h>
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+#include <avr/interrupt.h>
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+
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+#include "usiTwiSlave.h"
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+
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+#define HOLD_DIR DDB3
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+#define ATTK_DIR DDB4
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+#define LED_DIR DDB1
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+
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+#define HOLD_PIN PINB3
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+#define ATTK_PIN PINB4
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+#define LED_PIN PINB1
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+
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+// Opcodes
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+enum
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+{
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+ kSetPwm_Op = 0, // Set PWM duty/hz/div 0 {<duty> {<freq> {<div>}}} div:2=2,3=4,4=8,5=16,6=32,7=64,8=128,9=256,10=512,11=1024,12=2048,13=4096,14=8192,15=16384
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+ kNoteOnVel_Op = 1, // Turn on note 3 {<vel>}
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+ kNoteOnUsec_Op = 2, // Turn on note 4 {<coarse> {<fine> {<prescale>}}}
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+ kNoteOff_Op = 3, // Turn off note 5
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+ kSetReadAddr_Op = 4, // Set a read addr. 6 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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+ kWrite_Op = 5, // Set write 7 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
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+ kWriteTable_Op = 6, // Write table to EEprom 9
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+ kHoldDelay_Op = 7, // Set hold delay {<coarse> {<fine>}}
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+ kFlags_Op = 8, // Set flags variable
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+ kInvalid_Op = 9 //
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+};
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+
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+
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+enum
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+{
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+ kReg_Rd_Addr_idx = 0, // Next Reg Address to read
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+ kTable_Rd_Addr_idx = 1, // Next Table Address to read
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+ kEE_Rd_Addr_idx = 2, // Next EEPROM address to read
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+ kRead_Src_idx = 3, // kReg_Rd_Addr_idx=reg, kTable_Rd_Addr_idx=table, kEE_Rd_Addr_idx=eeprom
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+
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+ kReg_Wr_Addr_idx = 4, // Next Reg Address to write
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+ kTable_Wr_Addr_idx = 5, // Next Table Address to write
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+ kEE_Wr_Addr_idx = 6, // Next EEPROM address to write
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+ kWrite_Dst_idx = 7, // kReg_Wr_Addr_idx=reg, kTable_Wr_Addr_idx=table, kEE_Wr_Addr_idx=eeprom
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+
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+ kTmr_Coarse_idx = 8, //
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+ kTmr_Fine_idx = 9, //
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+ kTmr_Prescale_idx = 10, // Timer 0 clock divider: 1=1,2=8,3=64,4=256,5=1024 Default: 4 (16us)
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+
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+ kPwm_Duty_idx = 11, //
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+ kPwm_Freq_idx = 12, //
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+ kPwm_Div_idx = 13, //
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+
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+ kState_idx = 14, // 1=attk 2=hold
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+ kError_Code_idx = 15, // Error Code
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+ kMax_Coarse_Tmr_idx = 16, // Max. allowable coarse timer value
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+
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+ kDelay_Coarse_idx = 17, // (17,18)=2000 (0,6)=100
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+ kDelay_Fine_idx = 18,
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+
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+ kFlags_idx = 19,
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+
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+ kMax_idx
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+};
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+
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+enum
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+{
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+ kState_Attk_Fl = 1,
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+ kState_Hold_Fl = 2
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+};
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+
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+// ctl_regs[kFlags_idx] bits
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+enum
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+{
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+ kHoldOnAttk_Fl = 0x01
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+};
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+
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+volatile uint8_t ctl_regs[] =
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+{
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+ 0, // 0 (0-(kMax_idx-1)) Reg Read Addr
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+ 0, // 1 (0-255) Table Read Addr
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+ 0, // 2 (0-255) EE Read Addr
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+ kReg_Rd_Addr_idx, // 3 (0-2) Read source
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+
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+ 0, // 4 (0-(kMax_idx-1)) Reg Write Addr
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+ 0, // 5 (0-255) Table Write Addr
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+ 0, // 6 (0-255) EE Write Addr
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+ kReg_Wr_Addr_idx, // 7 (0-2) Write source
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+
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+ 5, // 8 (0-255) Timer 0 Coarse Value (20400 us)
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+ 0, // 9 (0-255) Timer 0 Fine Value
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+ 4, // 10 (1-5) 4=16us per tick
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+
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+ 127, // 11 (0-255) Pwm Duty cycle
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+ 255, // 12 (0-255) Pwm Frequency (123 Hz)
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+ 5, // 13 (0-15) Pwm clock div
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+
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+ 0, // 14 state flags 1=attk 2=hold (read/only)
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+ 0, // 15 (0-255) Error bit field
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+ 14, // 16 (0-255) Max allowable coarse timer count
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+
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+ 0, // 17 (0-255) Hold coarse delay
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+ 250, // 18 (0-255) Hold fine delay 0,6=100us 0,124=2000us w/ 16us Tmr0 tick
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+ 0 // 19 (0-255) Flags 1=hold-on-attack
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+
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+};
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+
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+// These registers are saved to Eeprom
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+uint8_t eeprom_addr[] =
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+{
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+ kTmr_Prescale_idx,
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+ kPwm_Duty_idx,
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+ kPwm_Freq_idx,
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+ kPwm_Div_idx
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+};
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+
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+
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+
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+#define tableN 256
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+uint8_t table[ tableN ]; // [ coarse_0,fine_0, coarse_1, fine_1, .... coarse_127,fine_127]
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+
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+
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+enum
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+{
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+ kInvalid_Read_Src_ErrFl = 0x01,
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+ kInvalid_Write_Dst_ErrFl = 0x02,
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+ kInvalid_Coarse_Tmr_ErrFl = 0x04
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+};
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+
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+#define set_error( flag ) ctl_regs[ kError_Code_idx ] |= (flag)
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// EEPROM
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+//
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+
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+void EEPROM_write(uint8_t ucAddress, uint8_t ucData)
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+{
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+ // Wait for completion of previous write
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+ while(EECR & (1<<EEPE))
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+ {}
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+
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+ EECR = (0<<EEPM1)|(0<<EEPM0); // Set Programming mode
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+ EEAR = ucAddress; // Set up address and data registers
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+ EEDR = ucData;
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+ EECR |= (1<<EEMPE); // Write logical one to EEMPE
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+ EECR |= (1<<EEPE); // Start eeprom write by setting EEPE
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+}
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+
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+uint8_t EEPROM_read(uint8_t ucAddress)
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+{
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+ // Wait for completion of previous write
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+ while(EECR & (1<<EEPE))
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+ {}
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+
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+ EEAR = ucAddress; // Set up address register
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+ EECR |= (1<<EERE); // Start eeprom read by writing EERE
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+ return EEDR; // Return data from data register
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+}
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+
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+void write_table()
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+{
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+ uint8_t i;
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+ uint8_t regN = sizeof(eeprom_addr);
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+
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+ // write the persistent registers
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+ for(i=0; i<regN; ++i)
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+ EEPROM_write( i, ctl_regs[ eeprom_addr[i] ] );
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+
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+ // write the table
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+ for(i=0; i<tableN; ++i)
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+ EEPROM_write( regN+i, table[i] );
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+}
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+
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+void load_table()
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+{
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+ uint8_t i;
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+ uint8_t regN = sizeof(eeprom_addr);
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+
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+ // read the persistent registers
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+ for(i=0; i<regN; ++i)
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+ ctl_regs[ eeprom_addr[i] ] = EEPROM_read(i);
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+
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+ // read the tabke
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+ for(i=0; i<tableN; ++i)
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+ table[i] = EEPROM_read(regN + i);
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+}
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+
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// Timer0
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+//
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+
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+uint16_t stage1_cnt = 0;
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+uint16_t stage2_cnt = 0;
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+uint8_t stage1_coarse_cnt = 0;
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+uint8_t stage1_fine_cnt = 0;
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+uint8_t stage2_coarse_cnt = 0;
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+uint8_t stage2_fine_cnt = 0;
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+uint8_t hold_beg_first_fl = 0;
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+
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+volatile uint8_t tmr0_state = 0; // current timer mode: 0=disabled 1=coarse mode, 2=fine mode
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+volatile uint8_t tmr0_coarse_cur = 0;
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+
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+
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+
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+
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+#define set_attack() do { ctl_regs[kState_idx] |= kState_Attk_Fl; PORTB |= _BV(ATTK_PIN); } while(0)
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+#define clear_attack() do { PORTB &= ~_BV(ATTK_PIN); ctl_regs[kState_idx] &= ~kState_Attk_Fl; } while(0)
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+
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+#define clear_hold() PORTB &= ~(_BV(HOLD_PIN))
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+#define set_hold() PORTB |= _BV(HOLD_PIN)
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+
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+
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+void hold_begin()
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+{
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+ // Reset the PWM counter to to OCR1C (PWM TOP) so that it immediately triggers
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+ // set_hold() and latches any new value for OCR1B (See: 12.2.2 Timer/Counter1 in PWM Mode)
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+ // If this is not done and OCR1B was modified the first pulse will have the incorrect length.
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+ TCNT1 = ctl_regs[kPwm_Freq_idx];
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+ TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // PWM interupt Enable interrupts
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+
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+ TCCR1 |= ctl_regs[ kPwm_Div_idx]; // 32us period (512 divider) prescaler
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+ GTCCR |= _BV(PSR1); // Force the pre-scale to be latched by setting PSR1
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+
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+}
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+
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+void hold_end()
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+{
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+ clear_attack();
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+ clear_hold();
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+ TIMSK &= ~_BV(OCIE0A); // Clear timer interrupt (shouldn't be necessary but doesn't hurt on during note-off message)
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+ TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // PWM interupt disable interrupts
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+
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+ TCCR1 = 0; // Stop the PWM timer by setting the pre-scale to 0
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+ GTCCR |= _BV(PSR1); // Force the pre-scale to be latched by setting PSR1
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+
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+}
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+
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+// Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
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+void tmr0_reset()
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+{
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+ uint16_t delayCnt = ctl_regs[ kDelay_Coarse_idx ];
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+ delayCnt = (delayCnt<<8) + ctl_regs[ kDelay_Fine_idx ];
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+
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+ uint16_t attkCnt = ctl_regs[ kTmr_Coarse_idx ];
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+ attkCnt = (attkCnt<<8) + ctl_regs[ kTmr_Fine_idx ];
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+
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+ if( attkCnt > delayCnt )
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+ {
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+ stage1_cnt = attkCnt - delayCnt;
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+ stage2_cnt = delayCnt;
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+ hold_beg_first_fl = 1;
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+ }
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+ else
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+ {
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+ stage1_cnt = attkCnt;
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+ stage2_cnt = delayCnt - attkCnt;
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+ hold_beg_first_fl = 0;
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+ }
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+
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+ stage1_coarse_cnt = stage1_cnt >> 8;
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+ stage1_fine_cnt = stage1_cnt & 0xff;
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+
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+ stage2_coarse_cnt = stage2_cnt >> 8;
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+ stage2_fine_cnt = stage2_cnt & 0xff;
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+
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+ tmr0_coarse_cur = 0; // clear the coarse time counter
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+
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+ // always start in mode=1 because even if coarse count==0
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+ // because a COMPA interrupt will be fired immediately when the
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+ // timer starts
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+ tmr0_state = 1;
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+ OCR0A = 0xff;
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+ TCNT0 = 0;
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+
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+ clear_hold(); // clear the hold pin
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+ set_attack(); // set the attack pin
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+
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+ TIMSK |= _BV(OCIE0A); // enable the timer interrupt
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+
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+ //if( ctl_regs[ kFlags_idx ] & kHoldOnAttk_Fl )
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+ // hold_begin();
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+
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+}
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+
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+ISR(TIMER0_COMPA_vect)
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+{
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+ switch( tmr0_state )
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+ {
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+ case 0: // timer disabled
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+ break;
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+
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+ case 1: // stage1 coarse mode
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+ // Note: the '+1' here is necessary to absorb an interrupt which is occurring
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+ // for an unknown reason. It must have something to do with resetting the
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+ // OCIE0A interrupt because it doesn't occur on the hold delay coarse timing.
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+ if( ++tmr0_coarse_cur >= stage1_coarse_cnt+1 )
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+ {
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+ tmr0_state = 2;
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+ OCR0A = stage1_fine_cnt;
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+ }
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+ break;
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+
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+ case 2: // stage1 fine mode complete
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+
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+ // if a coarse delay count exists then go into stage2 coarse mode
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+ if( stage2_coarse_cnt > 0 )
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334
|
+ {
|
|
335
|
+ tmr0_state = 3;
|
|
336
|
+ tmr0_coarse_cur = 0;
|
|
337
|
+ OCR0A = 0xff;
|
|
338
|
+ }
|
|
339
|
+ else // otherwise go into fine mode
|
|
340
|
+ {
|
|
341
|
+ tmr0_state = 4;
|
|
342
|
+ OCR0A = stage2_fine_cnt;
|
|
343
|
+ }
|
|
344
|
+
|
|
345
|
+ if( hold_beg_first_fl )
|
|
346
|
+ hold_begin(); // start hold PWM
|
|
347
|
+ else
|
|
348
|
+ clear_attack();
|
|
349
|
+
|
|
350
|
+ break;
|
|
351
|
+
|
|
352
|
+ case 3: // stage2 coarse mode
|
|
353
|
+ if( ++tmr0_coarse_cur >= stage2_coarse_cnt )
|
|
354
|
+ {
|
|
355
|
+ tmr0_state = 4;
|
|
356
|
+ OCR0A = stage2_fine_cnt;
|
|
357
|
+ }
|
|
358
|
+ break;
|
|
359
|
+
|
|
360
|
+ case 4: // stage2 fine mode complete
|
|
361
|
+ TIMSK &= ~_BV(OCIE0A); // clear timer interrupt
|
|
362
|
+ tmr0_state = 0;
|
|
363
|
+
|
|
364
|
+ if( hold_beg_first_fl )
|
|
365
|
+ clear_attack();
|
|
366
|
+ else
|
|
367
|
+ hold_begin();
|
|
368
|
+
|
|
369
|
+ //if( !(ctl_regs[ kFlags_idx ] & kHoldOnAttk_Fl) )
|
|
370
|
+ // hold_begin();
|
|
371
|
+ break;
|
|
372
|
+ }
|
|
373
|
+}
|
|
374
|
+
|
|
375
|
+
|
|
376
|
+
|
|
377
|
+void tmr0_init()
|
|
378
|
+{
|
|
379
|
+ TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
|
|
380
|
+ TCCR0A = 0; // Set the timer control registers to their default value
|
|
381
|
+ TCCR0B = 0;
|
|
382
|
+ TCCR0A |= 0x02; // CTC mode
|
|
383
|
+ TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
|
|
384
|
+ GTCCR |= _BV(PSR0); // Trigger the pre-scaler to be reset to the selected value
|
|
385
|
+}
|
|
386
|
+
|
|
387
|
+
|
|
388
|
+//------------------------------------------------------------------------------
|
|
389
|
+//------------------------------------------------------------------------------
|
|
390
|
+//------------------------------------------------------------------------------
|
|
391
|
+//
|
|
392
|
+// Pwm
|
|
393
|
+//
|
|
394
|
+// PWM is optimized to use pins OC1A ,~OC1A, OC1B, ~OC1B
|
|
395
|
+// but since these pins are not available this code uses
|
|
396
|
+// ISR's to redirect the output to PIN3
|
|
397
|
+
|
|
398
|
+void pwm1_update()
|
|
399
|
+{
|
|
400
|
+ OCR1B = ctl_regs[kPwm_Duty_idx]; // control duty cycle
|
|
401
|
+ OCR1C = ctl_regs[kPwm_Freq_idx]; // PWM frequency pre-scaler
|
|
402
|
+}
|
|
403
|
+
|
|
404
|
+
|
|
405
|
+// Called when TCNT1 == OCR1C.
|
|
406
|
+// At this point TCNT1 is reset to 0, new OCR1B values are latched from temp. loctaion to OCR1B
|
|
407
|
+ISR(TIMER1_OVF_vect)
|
|
408
|
+{
|
|
409
|
+ set_hold();
|
|
410
|
+}
|
|
411
|
+
|
|
412
|
+// Called when TCNT1 == OCR1B
|
|
413
|
+ISR(TIMER1_COMPB_vect)
|
|
414
|
+{
|
|
415
|
+ clear_hold();
|
|
416
|
+}
|
|
417
|
+
|
|
418
|
+
|
|
419
|
+void pwm1_init()
|
|
420
|
+{
|
|
421
|
+ DDRB |= _BV(HOLD_DIR); // setup PB3 as output
|
|
422
|
+
|
|
423
|
+ TCCR1 = 0; // Set the control registers to their default
|
|
424
|
+ GTCCR = 0;
|
|
425
|
+ GTCCR |= _BV(PWM1B); // Enable PWM B and disconnect output pins
|
|
426
|
+
|
|
427
|
+ pwm1_update();
|
|
428
|
+
|
|
429
|
+}
|
|
430
|
+
|
|
431
|
+//------------------------------------------------------------------------------
|
|
432
|
+//------------------------------------------------------------------------------
|
|
433
|
+//------------------------------------------------------------------------------
|
|
434
|
+
|
|
435
|
+// Tracks the current register pointer position
|
|
436
|
+volatile uint8_t reg_position = 0;
|
|
437
|
+const uint8_t reg_size = sizeof(ctl_regs);
|
|
438
|
+
|
|
439
|
+//
|
|
440
|
+// Read Request Handler
|
|
441
|
+//
|
|
442
|
+// This is called for each read request we receive, never put more
|
|
443
|
+// than one byte of data (with TinyWireS.send) to the send-buffer when
|
|
444
|
+// using this callback
|
|
445
|
+//
|
|
446
|
+
|
|
447
|
+void on_request()
|
|
448
|
+{
|
|
449
|
+ uint8_t val = 0;
|
|
450
|
+
|
|
451
|
+ switch( ctl_regs[ kRead_Src_idx ] )
|
|
452
|
+ {
|
|
453
|
+ case kReg_Rd_Addr_idx:
|
|
454
|
+ val = ctl_regs[ ctl_regs[kReg_Rd_Addr_idx] ];
|
|
455
|
+ break;
|
|
456
|
+
|
|
457
|
+ case kTable_Rd_Addr_idx:
|
|
458
|
+ val = table[ ctl_regs[kTable_Rd_Addr_idx] ];
|
|
459
|
+ break;
|
|
460
|
+
|
|
461
|
+ case kEE_Rd_Addr_idx:
|
|
462
|
+ val = EEPROM_read(ctl_regs[kEE_Rd_Addr_idx]);
|
|
463
|
+ break;
|
|
464
|
+
|
|
465
|
+ default:
|
|
466
|
+ set_error( kInvalid_Read_Src_ErrFl );
|
|
467
|
+ return;
|
|
468
|
+ }
|
|
469
|
+
|
|
470
|
+ usiTwiTransmitByte(val);
|
|
471
|
+
|
|
472
|
+ ctl_regs[ ctl_regs[ kRead_Src_idx ] ] += 1;
|
|
473
|
+
|
|
474
|
+}
|
|
475
|
+
|
|
476
|
+
|
|
477
|
+void _write_op( uint8_t* stack, uint8_t stackN )
|
|
478
|
+{
|
|
479
|
+ uint8_t stack_idx = 0;
|
|
480
|
+
|
|
481
|
+ if( stackN > 0 )
|
|
482
|
+ {
|
|
483
|
+ uint8_t src = stack[0] & 0x07;
|
|
484
|
+ uint8_t addr_fl = stack[0] & 0x08;
|
|
485
|
+
|
|
486
|
+ // verify the source value
|
|
487
|
+ if( src < kReg_Wr_Addr_idx || src > kEE_Wr_Addr_idx )
|
|
488
|
+ {
|
|
489
|
+ set_error( kInvalid_Write_Dst_ErrFl );
|
|
490
|
+ return;
|
|
491
|
+ }
|
|
492
|
+
|
|
493
|
+ // set the write source
|
|
494
|
+ stack_idx = 1;
|
|
495
|
+ ctl_regs[ kWrite_Dst_idx ] = src;
|
|
496
|
+
|
|
497
|
+ // if an address value was passed also ....
|
|
498
|
+ if( addr_fl && stackN > 1 )
|
|
499
|
+ {
|
|
500
|
+ stack_idx = 2;
|
|
501
|
+ ctl_regs[ src ] = stack[1];
|
|
502
|
+ }
|
|
503
|
+ }
|
|
504
|
+
|
|
505
|
+ //
|
|
506
|
+ for(; stack_idx<stackN; ++stack_idx)
|
|
507
|
+ {
|
|
508
|
+ uint8_t addr_idx = ctl_regs[ ctl_regs[kWrite_Dst_idx] ]++;
|
|
509
|
+ uint8_t val = stack[ stack_idx ];
|
|
510
|
+
|
|
511
|
+ switch( ctl_regs[ kWrite_Dst_idx ] )
|
|
512
|
+ {
|
|
513
|
+ case kReg_Wr_Addr_idx: ctl_regs[ addr_idx ] = val; break;
|
|
514
|
+ case kTable_Wr_Addr_idx: table[ addr_idx ] = val; break;
|
|
515
|
+ case kEE_Wr_Addr_idx: EEPROM_write( table[ addr_idx ], val); break;
|
|
516
|
+
|
|
517
|
+ default:
|
|
518
|
+ set_error( kInvalid_Write_Dst_ErrFl );
|
|
519
|
+ break;
|
|
520
|
+ }
|
|
521
|
+ }
|
|
522
|
+}
|
|
523
|
+
|
|
524
|
+//
|
|
525
|
+// The I2C data received -handler
|
|
526
|
+//
|
|
527
|
+// This needs to complete before the next incoming transaction (start,
|
|
528
|
+// data, restart/stop) on the bus does so be quick, set flags for long
|
|
529
|
+// running tasks to be called from the mainloop instead of running
|
|
530
|
+// them directly,
|
|
531
|
+//
|
|
532
|
+
|
|
533
|
+void on_receive( uint8_t byteN )
|
|
534
|
+{
|
|
535
|
+ PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
|
536
|
+
|
|
537
|
+ const uint8_t stackN = 16;
|
|
538
|
+ uint8_t stack_idx = 0;
|
|
539
|
+ uint8_t stack[ stackN ];
|
|
540
|
+ uint8_t i;
|
|
541
|
+
|
|
542
|
+ if (byteN < 1 || byteN > TWI_RX_BUFFER_SIZE)
|
|
543
|
+ {
|
|
544
|
+ // Sanity-check
|
|
545
|
+ return;
|
|
546
|
+ }
|
|
547
|
+
|
|
548
|
+ // get the register index to read/write
|
|
549
|
+ uint8_t op_id = usiTwiReceiveByte();
|
|
550
|
+
|
|
551
|
+ byteN--;
|
|
552
|
+
|
|
553
|
+ // If only one byte was received then this was a read request
|
|
554
|
+ // and the buffer pointer (reg_position) is now set to return the byte
|
|
555
|
+ // at this location on the subsequent call to on_request() ...
|
|
556
|
+ if(byteN)
|
|
557
|
+ {
|
|
558
|
+ while( byteN-- )
|
|
559
|
+ {
|
|
560
|
+ stack[stack_idx] = usiTwiReceiveByte();
|
|
561
|
+ ++stack_idx;
|
|
562
|
+ }
|
|
563
|
+ }
|
|
564
|
+
|
|
565
|
+ switch( op_id )
|
|
566
|
+ {
|
|
567
|
+ case kSetPwm_Op:
|
|
568
|
+ for(i=0; i<stack_idx && i<3; ++i)
|
|
569
|
+ ctl_regs[ kPwm_Duty_idx + i ] = stack[i];
|
|
570
|
+
|
|
571
|
+ pwm1_update();
|
|
572
|
+ break;
|
|
573
|
+
|
|
574
|
+
|
|
575
|
+ case kNoteOnUsec_Op:
|
|
576
|
+ for(i=0; i<stack_idx && i<3; ++i)
|
|
577
|
+ ctl_regs[ kTmr_Coarse_idx + i ] = stack[i];
|
|
578
|
+
|
|
579
|
+ // validate the coarse error value
|
|
580
|
+ if( ctl_regs[ kTmr_Coarse_idx ] > ctl_regs[ kMax_Coarse_Tmr_idx ])
|
|
581
|
+ {
|
|
582
|
+ ctl_regs[ kTmr_Coarse_idx ] = ctl_regs[ kMax_Coarse_Tmr_idx ];
|
|
583
|
+ set_error( kInvalid_Coarse_Tmr_ErrFl );
|
|
584
|
+ }
|
|
585
|
+ // if a prescaler was included then the timer needs to be re-initialized
|
|
586
|
+ if( i == 3 )
|
|
587
|
+ {
|
|
588
|
+ cli();
|
|
589
|
+ tmr0_init();
|
|
590
|
+ sei();
|
|
591
|
+ }
|
|
592
|
+
|
|
593
|
+ tmr0_reset();
|
|
594
|
+ break;
|
|
595
|
+
|
|
596
|
+ case kNoteOff_Op:
|
|
597
|
+ hold_end();
|
|
598
|
+ break;
|
|
599
|
+
|
|
600
|
+ case kSetReadAddr_Op:
|
|
601
|
+ if( stack_idx > 0 )
|
|
602
|
+ {
|
|
603
|
+ ctl_regs[ kRead_Src_idx ] = stack[0];
|
|
604
|
+
|
|
605
|
+ if( stack_idx > 1 )
|
|
606
|
+ ctl_regs[ ctl_regs[ kRead_Src_idx ] ] = stack[1];
|
|
607
|
+ }
|
|
608
|
+ break;
|
|
609
|
+
|
|
610
|
+ case kWrite_Op:
|
|
611
|
+ _write_op( stack, stack_idx );
|
|
612
|
+ break;
|
|
613
|
+
|
|
614
|
+ case kWriteTable_Op:
|
|
615
|
+ write_table();
|
|
616
|
+ break;
|
|
617
|
+
|
|
618
|
+ case kHoldDelay_Op:
|
|
619
|
+ for(i=0; i<stack_idx && i<2; ++i)
|
|
620
|
+ ctl_regs[ kDelay_Coarse_idx + i ] = stack[i];
|
|
621
|
+
|
|
622
|
+ break;
|
|
623
|
+
|
|
624
|
+ case kFlags_Op:
|
|
625
|
+ ctl_regs[ kFlags_idx ] = stack[0];
|
|
626
|
+
|
|
627
|
+ }
|
|
628
|
+}
|
|
629
|
+
|
|
630
|
+
|
|
631
|
+int main(void)
|
|
632
|
+{
|
|
633
|
+ cli(); // mask all interupts
|
|
634
|
+
|
|
635
|
+ DDRB |= _BV(ATTK_DIR) + _BV(HOLD_DIR) + _BV(LED_DIR); // setup PB4,PB3,PB1 as output
|
|
636
|
+ PORTB &= ~(_BV(ATTK_PIN) + _BV(HOLD_PIN) + _BV(LED_PIN)); // clear output pins
|
|
637
|
+
|
|
638
|
+ tmr0_init();
|
|
639
|
+ pwm1_init();
|
|
640
|
+
|
|
641
|
+ // setup i2c library
|
|
642
|
+ usi_onReceiverPtr = on_receive;
|
|
643
|
+ usi_onRequestPtr = on_request;
|
|
644
|
+ usiTwiSlaveInit(I2C_SLAVE_ADDRESS);
|
|
645
|
+
|
|
646
|
+ sei();
|
|
647
|
+
|
|
648
|
+ PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
|
649
|
+ _delay_ms(1000);
|
|
650
|
+ PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
|
651
|
+
|
|
652
|
+
|
|
653
|
+ while(1)
|
|
654
|
+ {
|
|
655
|
+
|
|
656
|
+ if (!usi_onReceiverPtr)
|
|
657
|
+ {
|
|
658
|
+ // no onReceive callback, nothing to do...
|
|
659
|
+ continue;
|
|
660
|
+ }
|
|
661
|
+
|
|
662
|
+ if (!(USISR & ( 1 << USIPF )))
|
|
663
|
+ {
|
|
664
|
+ // Stop not detected
|
|
665
|
+ continue;
|
|
666
|
+ }
|
|
667
|
+
|
|
668
|
+
|
|
669
|
+ uint8_t amount = usiTwiAmountDataInReceiveBuffer();
|
|
670
|
+ if (amount == 0)
|
|
671
|
+ {
|
|
672
|
+ // no data in buffer
|
|
673
|
+ continue;
|
|
674
|
+ }
|
|
675
|
+
|
|
676
|
+
|
|
677
|
+ usi_onReceiverPtr(amount);
|
|
678
|
+
|
|
679
|
+
|
|
680
|
+ }
|
|
681
|
+ return 0;
|
|
682
|
+}
|
|
683
|
+
|
|
684
|
+
|
|
685
|
+
|