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@@ -1,10 +1,14 @@
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+// w 60 0 1 10 : w i2c_addr SetPWM enable duty_val
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+// w 60 5 12 8 32 : w i2c_addr write addrFl|src coarse_val
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+// w 60 4 0 5 : w i2c_addr read src read_addr (set the read address to register 5)
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+// r 60 4 3 : r i2c_addr <dum> cnt (read the first 3 reg's beginning w/ 5)
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/*
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AT TINY 85
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+--\/--+
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RESET _| 1 8 |_ +5V
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- ~OC1B HOLD DDB3 _| 2 7 |_ SCL
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+ ~OC1B HOLD DDB3 _| 2 7 |_ SCL yellow
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OC1B ONSET DDB4 _| 3 6 |_ DDB1 LED
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- GND _| 4 5 |_ SDA
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+ GND _| 4 5 |_ SDA orange
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+------+
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* = Serial and/or programming pins on Arduino as ISP
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*/
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@@ -12,6 +16,7 @@
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// This program acts as the device (slave) for the control program i2c/a2a/c_ctl
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#define F_CPU 8000000L
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+
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#include <stdio.h>
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#include <avr/io.h>
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#include <util/delay.h>
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@@ -19,50 +24,98 @@
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#include "usiTwiSlave.h"
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+#define HOLD_DIR DDB3
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+#define ATTK_DIR DDB4
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+#define LED_DIR DDB1
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+
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+#define HOLD_PIN PINB3
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+#define ATTK_PIN PINB4
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+#define LED_PIN PINB1
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-#define I2C_SLAVE_ADDRESS 0x8 // the 7-bit address (remember to change this when adapting this example)
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+// Opcodes
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+enum
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+{
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+ kSetPwm_Op = 0, // Set PWM registers 0 {<enable> {<duty> {<freq>}}}
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+ kNoteOnVel_Op = 1, // Turn on note 1 {<vel>}
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+ kNoteOnUsec_Op = 2, // Turn on note 2 {<coarse> {<fine> {<prescale>}}}
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+ kNoteOff_Op = 3, // Turn off note 3
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+ kRead_Op = 4, // Read a value 4 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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+ kWrite_Op = 5, // Set write 5 {<addrfl|src> {addr} {<value0> ... {<valueN>}}
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+ kInvalid_Op = 6 // addrFl:0x80 src: 4=reg 5=table 6=eeprom
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+};
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enum
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{
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- kTmr0_Prescale_idx = 0, // Timer 0 clock divider: 1=1,2=8,3=64,4=256,5=1024
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- kTmr0_Coarse_idx = 1, //
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- kTmr0_Fine_idx = 2, //
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- kPWM0_Duty_idx = 3, //
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- kPWM0_Freq_idx = 4, // 1-4 = clock divider=1=1,2=8,3=64,4=256,5=1024
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- kCS13_10_idx = 5, // Timer 1 Prescalar (CS13,CS12,CS11,CS10) from Table 12-5 pg 89 (0-15) prescaler = pow(2,val-1), 0=stop,1=1,2=2,3=4,4=8,....14=8192,15=16384 pre_scaled_hz = clock_hz/value
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- kTmr1_Coarse_idx = 6, // count of times timer0 count to 255 before OCR1C is set to Tmr0_Fine
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- kTmr1_Fine_idx = 7, // OCR1C timer match value
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- kPWM1_Duty_idx = 8, //
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- kPWM1_Freq_idx = 9, //
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- kTable_Addr_idx = 10, // Next table address to read/write
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- kTable_Coarse_idx = 11, // Next table coarse value to read/write
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- kTable_Fine_idx = 12, // Next table fine value to read/write
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+ kReg_Rd_Addr_idx = 0, // Next Reg Address to read
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+ kTable_Rd_Addr_idx = 1, // Next Table Address to read
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+ kEE_Rd_Addr_idx = 2, // Next EEPROM address to read
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+ kRead_Src_idx = 3, // kReg_Rd_Addr_idx=reg, kTable_Rd_Addr_idx=table, kEE_Rd_Addr_idx=eeprom
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+
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+ kReg_Wr_Addr_idx = 4, // Next Reg Address to write
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+ kTable_Wr_Addr_idx = 5, // Next Table Address to write
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+ kEE_Wr_Addr_idx = 6, // Next EEPROM address to write
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+ kWrite_Dst_idx = 7, // kReg_Wr_Addr_idx=reg, kTable_Wr_Addr_idx=table, kEE_Wr_Addr_idx=eeprom
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+
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+ kTmr_Coarse_idx = 8, //
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+ kTmr_Fine_idx = 9, //
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+ kTmr_Prescale_idx = 10, // Timer 0 clock divider: 1=1,2=8,3=64,4=256,5=1024 Default: 8 (32us)
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+
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+ kPwm_Enable_idx = 11, //
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+ kPwm_Duty_idx = 12, //
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+ kPwm_Freq_idx = 13, //
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+
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+ kMode_idx = 14, // 1=repeat 2=pwm
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+ kState_idx = 15, // 1=attk 2=hold
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+ kError_Code_idx = 16, // Error Code
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kMax_idx
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};
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+enum
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+{
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+ kTmr_Repeat_Fl= 1,
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+ kTmr_Pwm_Fl = 2,
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+ kAttk_Fl = 1,
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+ kHold_Fl = 2
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+};
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+
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+// Flags:
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+// 1=Repeat: 1=Timer and PWM are free running. This allows testing with LED's. 0=Timer triggers does not reset on time out.
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+// 2=PWM: On timer timeout 1=PWM HOLD 0=Set HOLD
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volatile uint8_t ctl_regs[] =
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{
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- 4, // 0 (1-5) 4=32us per tick
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- 123, // 1 (0-255) Timer 0 Coarse Value
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- 8, // 2 (0-255) Timer 0 Fine Value
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- 127, // 3 (0-255) Duty cycle
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- 4, // 4 (1-4) PWM Frequency (clock pre-scaler)
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- 9, // 5 9=32 us period w/ 8Mhz clock (timer tick rate)
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- 123, // 6 (0-255) Tmr1_Coarse count of times timer count to 255 before loading Tmr0_Minor for final count.
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- 8, // 7 (0-254) Tmr1_Fine OCR1C value on final phase before triggering timer
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- 127, // 8 (0-255) PWM1 Duty cycle
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- 254, // 9 (0-255) PWM1 Frequency (123 hz)
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- 0, // 10 (0-127) Next table addr to read/write
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- 0, // 11 (0-255) Next table coarse value to write
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- 0, // 12 (0-255) Next table fine value to write
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+ 0, // 0 (0-(kMax_idx-1)) Reg Read Addr
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+ 0, // 1 (0-255) Table Read Addr
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+ 0, // 2 (0-255) EE Read Addr
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+ kReg_Rd_Addr_idx, // 3 (0-2) Read source
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+ 0, // 4 (0-(kMax_idx-1)) Reg Write Addr
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+ 0, // 5 (0-255) Table Write Addr
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+ 0, // 6 (0-255) EE Write Addr
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+ kReg_Wr_Addr_idx, // 7 (0-2) Write source
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+ 123, // 8 (0-255) Timer 0 Coarse Value
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+ 8, // 9 (0-255) Timer 0 Fine Value
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+ 4, // 10 (1-5) 4=32us per tick
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+ 1, // 11 (0-1) Pwm Enable Flag
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+ 127, // 12 (0-255) Pwm Duty cycle
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+ 254, // 13 (0-255) Pwm Frequency (123 hz)
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+ 0, // 14 mode flags 1=Repeat 2=PWM
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+ 0, // 15 state flags 1=attk 2=hold
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+ 0, // 16 (0-255) Error bit field
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};
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#define tableN 256
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-uint8_t table[ tableN ];
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+uint8_t table[ tableN ]; // [ coarse_0,fine_0, coarse_1, fine_1, .... coarse_127,fine_127]
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+enum
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+{
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+ kInvalid_Read_Src_ErrFl = 0x01,
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+ kInvalid_Write_Dst_ErrFl = 0x02
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+};
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+
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+#define set_error( flag ) ctl_regs[ kError_Code_idx ] |= (flag)
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+
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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@@ -113,7 +166,7 @@ uint8_t EEPROM_read(uint8_t ucAddress)
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// r 8 kTable_Coarse_idx -> 127
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// r 8 kTable_Fine_idx -> 64
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-
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+/*
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#define eeprom_addr( addr ) (kMax_idx + (addr))
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void table_write_cur_value( void )
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@@ -138,19 +191,7 @@ void table_load( void )
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table[tbl_addr+1] = EEPROM_read( eeprom_addr(tbl_addr+1) );
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}
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}
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-
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-void restore_memory_from_eeprom( void )
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-{
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- /*
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- uint8_t i;
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- for(i=0; i<kMax_idx; ++i)
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- {
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- ctl_regs[i] = EEPROM_read( eeprom_addr( i ) );
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- }
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- */
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-
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- table_load();
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-}
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+*/
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//------------------------------------------------------------------------------
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@@ -163,11 +204,15 @@ void restore_memory_from_eeprom( void )
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204
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volatile uint8_t tmr0_state = 0; // 0=disabled 1=coarse mode, 2=fine mode
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volatile uint8_t tmr0_coarse_cur = 0;
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206
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+#define set_attack() do { ctl_regs[kState_idx] |= kAttk_Fl; PORTB |= _BV(ATTK_PIN); } while(0)
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+#define clear_attack() do { PORTB &= ~_BV(ATTK_PIN); ctl_regs[kState_idx] &= ~kAttk_Fl; } while(0)
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+
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+
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211
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// Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
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212
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void tmr0_reset()
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168
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213
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{
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169
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214
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// if a coarse count exists then go into coarse mode
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- if( ctl_regs[kTmr0_Coarse_idx] > 0 )
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+ if( ctl_regs[kTmr_Coarse_idx] > 0 )
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216
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{
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172
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217
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tmr0_state = 1;
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218
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OCR0A = 0xff;
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@@ -175,10 +220,14 @@ void tmr0_reset()
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220
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else // otherwise go into fine mode
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221
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{
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177
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222
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tmr0_state = 2;
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178
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- OCR0A = ctl_regs[kTmr0_Fine_idx];
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223
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+ OCR0A = ctl_regs[kTmr_Fine_idx];
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179
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224
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}
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180
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225
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181
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- tmr0_coarse_cur = 0;
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226
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+ tmr0_coarse_cur = 0;
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+
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+ ctl_regs[kState_idx] |= kAttk_Fl; // set the attack state
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229
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+ PORTB |= _BV(ATTK_PIN); // set the attack pin
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230
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+ TIMSK |= _BV(OCIE0A); // enable the timer interrupt
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231
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}
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232
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184
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233
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ISR(TIMER0_COMPA_vect)
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@@ -191,18 +240,50 @@ ISR(TIMER0_COMPA_vect)
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191
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240
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192
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241
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case 1:
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193
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242
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// coarse mode
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194
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- if( ++tmr0_coarse_cur >= ctl_regs[kTmr0_Coarse_idx] )
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243
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+ if( ++tmr0_coarse_cur >= ctl_regs[kTmr_Coarse_idx] )
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195
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244
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{
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196
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245
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tmr0_state = 2;
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197
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- OCR0A = ctl_regs[kTmr0_Fine_idx];
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246
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+ OCR0A = ctl_regs[kTmr_Fine_idx];
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198
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247
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}
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199
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248
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break;
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200
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249
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201
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250
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case 2:
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202
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251
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// fine mode
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203
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- PINB = _BV(PINB4); // writes to PINB toggle the pins
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204
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252
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205
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- tmr0_reset(); // restart the timer
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253
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+ // If in repeat mode
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254
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+ if(ctl_regs[kMode_idx] & kTmr_Repeat_Fl)
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255
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+ {
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256
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+ uint8_t fl = ctl_regs[kState_idx] & kAttk_Fl;
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257
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+
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258
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+ tmr0_reset(); // restart the timer
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259
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+
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260
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+ // ATTK_PIN is always set after tmr0_reset() but we need to toggle in 'repeat' mode
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261
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+ if( fl )
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262
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+ {
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263
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+ clear_attack();
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264
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+ }
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265
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+
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266
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+ // In repeat mode we run the PWM output continuously
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267
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+ TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // Enable PWM interrupts
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268
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+
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269
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+ }
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270
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+ else // not in repeat mode
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+ {
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272
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+ clear_attack();
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+
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274
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+ if( ctl_regs[kMode_idx] & kTmr_Pwm_Fl)
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275
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+ {
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276
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+ TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // PWM interupt Enable interrupts
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277
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+ }
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+ else
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+ {
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280
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+ PORTB |= _BV(HOLD_PIN); // set the HOLD pin
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+ }
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282
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+
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283
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+ TIMSK &= ~_BV(OCIE0A); // clear timer interrupt
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+
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285
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+ }
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286
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+
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287
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break;
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288
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}
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289
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}
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@@ -212,144 +293,42 @@ void timer0_init()
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212
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293
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{
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213
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294
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TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
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214
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295
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TCCR0A |= 0x02; // CTC mode
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215
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- TCCR0B |= ctl_regs[kTmr0_Prescale_idx]; // set the prescaler
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296
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+ TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
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216
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297
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217
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298
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GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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218
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299
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219
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- tmr0_reset(); // set the timers starting state
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220
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-
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221
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- TIMSK |= _BV(OCIE0A); // Enable interrupt TIMER1_OVF
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222
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-
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223
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-}
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300
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+ //tmr0_reset(); // set the timers starting state
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224
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301
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225
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302
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226
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-//------------------------------------------------------------------------------
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-//------------------------------------------------------------------------------
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-//------------------------------------------------------------------------------
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229
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-//
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230
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-// PWM (Timer0)
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231
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-//
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232
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-
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233
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-void pwm0_update()
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234
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-{
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235
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- OCR0B = ctl_regs[kPWM0_Duty_idx]; // 50% duty cycle
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236
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- TCCR0B |= ctl_regs[kPWM0_Freq_idx]; // PWM frequency pre-scaler
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237
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-}
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238
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-
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239
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-void pwm0_init()
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240
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-{
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241
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- // WGM[1:0] = 3 (TOP=255)
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242
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- // OCR0B = duty cycle (0-100%)
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243
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- // COM0A[1:0] = 2 non-inverted
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244
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- //
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245
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-
|
246
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- TCCR0A |= 0x20 + 3; // 0x20=non-inverting 3=WGM bits Fast-PWM mode (0=Bot 255=Top)
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247
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- TCCR0B |= 0x00 + 4; // 3=256 pre-scaler 122Hz=1Mghz/(v*256) where v=64
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248
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-
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249
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- GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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250
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-
|
251
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- pwm0_update();
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252
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-
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253
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-
|
254
|
|
- DDRB |= _BV(DDB1); // set direction on
|
255
|
303
|
}
|
256
|
304
|
|
257
|
305
|
|
258
|
|
-
|
259
|
306
|
//------------------------------------------------------------------------------
|
260
|
307
|
//------------------------------------------------------------------------------
|
261
|
308
|
//------------------------------------------------------------------------------
|
262
|
309
|
//
|
263
|
|
-// Timer1
|
|
310
|
+// Pwm
|
264
|
311
|
//
|
|
312
|
+// PWM is optimized to use pins OC1A ,~OC1A, OC1B, ~OC1B
|
|
313
|
+// but since these pins are not available this code uses
|
|
314
|
+// ISR's to redirect the output to PIN3
|
265
|
315
|
|
266
|
|
-volatile uint8_t tmr1_state = 0;
|
267
|
|
-volatile uint8_t tmr1_coarse_cur = 0;
|
268
|
|
-static uint8_t tmr1_init_fl = 0;
|
269
|
|
-
|
270
|
|
-void tmr1_reset()
|
|
316
|
+void pwm1_update()
|
271
|
317
|
{
|
272
|
|
- if( ctl_regs[kTmr1_Coarse_idx] > 0 )
|
273
|
|
- {
|
274
|
|
- tmr1_state = 1;
|
275
|
|
- OCR1C = 254;
|
276
|
|
- }
|
277
|
|
- else
|
278
|
|
- {
|
279
|
|
- tmr1_state = 2;
|
280
|
|
- OCR1C = ctl_regs[kTmr1_Fine_idx];
|
281
|
|
- }
|
282
|
|
-
|
283
|
|
- tmr1_coarse_cur = 0;
|
|
318
|
+ OCR1B = ctl_regs[kPwm_Duty_idx]; // control duty cycle
|
|
319
|
+ OCR1C = ctl_regs[kPwm_Freq_idx]; // PWM frequency pre-scaler
|
284
|
320
|
}
|
285
|
321
|
|
286
|
|
-ISR(TIMER1_OVF_vect)
|
287
|
|
-{
|
288
|
|
- if( !tmr1_init_fl )
|
289
|
|
- {
|
290
|
|
- PORTB |= _BV(PINB3); // set PWM pin
|
291
|
|
- }
|
292
|
|
- else
|
293
|
|
- {
|
294
|
|
- switch( tmr1_state )
|
295
|
|
- {
|
296
|
|
-
|
297
|
|
- case 0:
|
298
|
|
- // disabled
|
299
|
|
- break;
|
300
|
|
-
|
301
|
|
- case 1:
|
302
|
|
- // coarse mode
|
303
|
|
- if( ++tmr1_coarse_cur >= ctl_regs[kTmr1_Coarse_idx] )
|
304
|
|
- {
|
305
|
|
- tmr1_state = 2;
|
306
|
|
- OCR1C = ctl_regs[kTmr1_Fine_idx];
|
307
|
|
- }
|
308
|
|
- break;
|
309
|
322
|
|
310
|
|
- case 2:
|
311
|
|
- // fine mode
|
312
|
|
- PINB = _BV(PINB4); // writes to PINB toggle the pins
|
313
|
323
|
|
314
|
|
- tmr1_reset();
|
315
|
|
- break;
|
316
|
|
- }
|
317
|
|
- }
|
318
|
|
-}
|
319
|
|
-
|
320
|
|
-void timer1_init()
|
321
|
|
-{
|
322
|
|
- TIMSK &= ~_BV(TOIE1); // Disable interrupt TIMER1_OVF
|
323
|
|
- OCR1A = 255; // Set to anything greater than OCR1C (the counter never gets here.)
|
324
|
|
- TCCR1 |= _BV(CTC1); // Reset TCNT1 to 0 when TCNT1==OCR1C
|
325
|
|
- TCCR1 |= _BV(PWM1A); // Enable PWM A (to generate overflow interrupts)
|
326
|
|
- TCCR1 |= ctl_regs[kCS13_10_idx] & 0x0f; //
|
327
|
|
- GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
|
328
|
|
-
|
329
|
|
- tmr1_reset();
|
330
|
|
- tmr1_init_fl = 1;
|
331
|
|
- TIMSK |= _BV(TOIE1); // Enable interrupt TIMER1_OVF
|
332
|
|
-}
|
333
|
|
-
|
334
|
|
-//------------------------------------------------------------------------------
|
335
|
|
-//------------------------------------------------------------------------------
|
336
|
|
-//------------------------------------------------------------------------------
|
337
|
|
-//
|
338
|
|
-// PWM1
|
339
|
|
-//
|
340
|
|
-// PWM is optimized to use pins OC1A ,~OC1A, OC1B, ~OC1B but this code
|
341
|
|
-// but since these pins are not available this code uses
|
342
|
|
-// ISR's to redirect the output to PIN3
|
343
|
|
-
|
344
|
|
-void pwm1_update()
|
|
324
|
+ISR(TIMER1_OVF_vect)
|
345
|
325
|
{
|
346
|
|
- OCR1B = ctl_regs[kPWM1_Duty_idx]; // control duty cycle
|
347
|
|
- OCR1C = ctl_regs[kPWM1_Freq_idx]; // PWM frequency pre-scaler
|
|
326
|
+ PORTB |= _BV(HOLD_PIN); // set PWM pin
|
348
|
327
|
}
|
349
|
328
|
|
350
|
329
|
ISR(TIMER1_COMPB_vect)
|
351
|
330
|
{
|
352
|
|
- PORTB &= ~(_BV(PINB3)); // clear PWM pin
|
|
331
|
+ PORTB &= ~(_BV(HOLD_PIN)); // clear PWM pin
|
353
|
332
|
}
|
354
|
333
|
|
355
|
334
|
|
|
@@ -357,7 +336,7 @@ void pwm1_init()
|
357
|
336
|
{
|
358
|
337
|
TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // Disable interrupts
|
359
|
338
|
|
360
|
|
- DDRB |= _BV(DDB3); // setup PB3 as output
|
|
339
|
+ DDRB |= _BV(HOLD_DIR); // setup PB3 as output
|
361
|
340
|
|
362
|
341
|
// set on TCNT1 == 0 // happens when TCNT1 matches OCR1C
|
363
|
342
|
// clr on OCR1B == TCNT // happens when TCNT1 matches OCR1B
|
|
@@ -367,11 +346,6 @@ void pwm1_init()
|
367
|
346
|
GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
|
368
|
347
|
|
369
|
348
|
pwm1_update();
|
370
|
|
-
|
371
|
|
- TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // Enable interrupts
|
372
|
|
-
|
373
|
|
-
|
374
|
|
-
|
375
|
349
|
}
|
376
|
350
|
|
377
|
351
|
//------------------------------------------------------------------------------
|
|
@@ -389,37 +363,83 @@ const uint8_t reg_size = sizeof(ctl_regs);
|
389
|
363
|
// than one byte of data (with TinyWireS.send) to the send-buffer when
|
390
|
364
|
// using this callback
|
391
|
365
|
//
|
|
366
|
+
|
392
|
367
|
void on_request()
|
393
|
368
|
{
|
394
|
369
|
uint8_t val = 0;
|
395
|
370
|
|
396
|
|
- switch( reg_position )
|
|
371
|
+ switch( ctl_regs[ kRead_Src_idx ] )
|
397
|
372
|
{
|
398
|
|
- case kTable_Coarse_idx:
|
399
|
|
- val = table[ ctl_regs[kTable_Addr_idx]*2 + 0 ];
|
|
373
|
+ case kReg_Rd_Addr_idx:
|
|
374
|
+ val = ctl_regs[ ctl_regs[kReg_Rd_Addr_idx] ];
|
400
|
375
|
break;
|
401
|
376
|
|
402
|
|
- case kTable_Fine_idx:
|
403
|
|
- val = table[ ctl_regs[kTable_Addr_idx]*2 + 1 ];
|
|
377
|
+ case kTable_Rd_Addr_idx:
|
|
378
|
+ val = table[ ctl_regs[kTable_Rd_Addr_idx] ];
|
|
379
|
+ break;
|
|
380
|
+
|
|
381
|
+ case kEE_Rd_Addr_idx:
|
|
382
|
+ val = EEPROM_read(ctl_regs[kEE_Rd_Addr_idx]);
|
404
|
383
|
break;
|
405
|
|
-
|
406
|
|
- default:
|
407
|
|
- // read and transmit the requestd position
|
408
|
|
- val = ctl_regs[reg_position];
|
409
|
384
|
|
|
385
|
+ default:
|
|
386
|
+ set_error( kInvalid_Read_Src_ErrFl );
|
|
387
|
+ return;
|
410
|
388
|
}
|
411
|
389
|
|
412
|
390
|
usiTwiTransmitByte(val);
|
|
391
|
+
|
|
392
|
+ ctl_regs[ ctl_regs[ kRead_Src_idx ] ] += 1;
|
|
393
|
+
|
|
394
|
+}
|
|
395
|
+
|
|
396
|
+
|
|
397
|
+void _write_op( uint8_t* stack, uint8_t stackN )
|
|
398
|
+{
|
|
399
|
+ uint8_t stack_idx = 0;
|
413
|
400
|
|
414
|
|
- // Increment the reg position on each read, and loop back to zero
|
415
|
|
- reg_position++;
|
416
|
|
- if (reg_position >= reg_size)
|
|
401
|
+ if( stackN > 0 )
|
417
|
402
|
{
|
418
|
|
- reg_position = 0;
|
|
403
|
+ uint8_t src = stack[0] & 0x07;
|
|
404
|
+ uint8_t addr_fl = stack[0] & 0x08;
|
|
405
|
+
|
|
406
|
+ // verify the source value
|
|
407
|
+ if( src < kReg_Wr_Addr_idx || src > kEE_Wr_Addr_idx )
|
|
408
|
+ {
|
|
409
|
+ set_error( kInvalid_Write_Dst_ErrFl );
|
|
410
|
+ return;
|
|
411
|
+ }
|
|
412
|
+
|
|
413
|
+ // set the write source
|
|
414
|
+ stack_idx = 1;
|
|
415
|
+ ctl_regs[ kWrite_Dst_idx ] = src;
|
|
416
|
+
|
|
417
|
+ // if an address value was passed also ....
|
|
418
|
+ if( addr_fl && stackN > 1 )
|
|
419
|
+ {
|
|
420
|
+ stack_idx = 2;
|
|
421
|
+ ctl_regs[ src ] = stack[1];
|
|
422
|
+ }
|
419
|
423
|
}
|
420
|
|
-
|
421
|
|
-}
|
422
|
424
|
|
|
425
|
+ //
|
|
426
|
+ for(; stack_idx<stackN; ++stack_idx)
|
|
427
|
+ {
|
|
428
|
+ uint8_t addr_idx = ctl_regs[ ctl_regs[kWrite_Dst_idx] ]++;
|
|
429
|
+ uint8_t val = stack[ stack_idx ];
|
|
430
|
+
|
|
431
|
+ switch( ctl_regs[ kWrite_Dst_idx ] )
|
|
432
|
+ {
|
|
433
|
+ case kReg_Wr_Addr_idx: ctl_regs[ addr_idx ] = val; break;
|
|
434
|
+ case kTable_Wr_Addr_idx: table[ addr_idx ] = val; break;
|
|
435
|
+ case kEE_Wr_Addr_idx: EEPROM_write( table[ addr_idx ], val); break;
|
|
436
|
+
|
|
437
|
+ default:
|
|
438
|
+ set_error( kInvalid_Write_Dst_ErrFl );
|
|
439
|
+ break;
|
|
440
|
+ }
|
|
441
|
+ }
|
|
442
|
+}
|
423
|
443
|
|
424
|
444
|
//
|
425
|
445
|
// The I2C data received -handler
|
|
@@ -432,87 +452,80 @@ void on_request()
|
432
|
452
|
|
433
|
453
|
void on_receive( uint8_t byteN )
|
434
|
454
|
{
|
435
|
|
- if (byteN < 1)
|
436
|
|
- {
|
437
|
|
- // Sanity-check
|
438
|
|
- return;
|
439
|
|
- }
|
440
|
|
- if (byteN > TWI_RX_BUFFER_SIZE)
|
441
|
|
- {
|
442
|
|
- // Also insane number
|
443
|
|
- return;
|
444
|
|
- }
|
|
455
|
+ PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
|
456
|
+
|
|
457
|
+ const uint8_t stackN = 16;
|
|
458
|
+ uint8_t stack_idx = 0;
|
|
459
|
+ uint8_t stack[ stackN ];
|
|
460
|
+ uint8_t i;
|
|
461
|
+
|
|
462
|
+ if (byteN < 1 || byteN > TWI_RX_BUFFER_SIZE)
|
|
463
|
+ {
|
|
464
|
+ // Sanity-check
|
|
465
|
+ return;
|
|
466
|
+ }
|
445
|
467
|
|
446
|
|
- // get the register index to read/write
|
447
|
|
- reg_position = usiTwiReceiveByte();
|
|
468
|
+ // get the register index to read/write
|
|
469
|
+ uint8_t op_id = usiTwiReceiveByte();
|
448
|
470
|
|
449
|
|
- byteN--;
|
|
471
|
+ byteN--;
|
450
|
472
|
|
451
|
|
- // If only one byte was received then this was a read request
|
452
|
|
- // and the buffer pointer (reg_position) is now set to return the byte
|
453
|
|
- // at this location on the subsequent call to on_request() ...
|
454
|
|
- if (!byteN)
|
455
|
|
- {
|
456
|
|
- return;
|
|
473
|
+ // If only one byte was received then this was a read request
|
|
474
|
+ // and the buffer pointer (reg_position) is now set to return the byte
|
|
475
|
+ // at this location on the subsequent call to on_request() ...
|
|
476
|
+ if(byteN)
|
|
477
|
+ {
|
|
478
|
+ while( byteN-- )
|
|
479
|
+ {
|
|
480
|
+ stack[stack_idx] = usiTwiReceiveByte();
|
|
481
|
+ ++stack_idx;
|
457
|
482
|
}
|
|
483
|
+ }
|
|
484
|
+
|
|
485
|
+ switch( op_id )
|
|
486
|
+ {
|
|
487
|
+ case kSetPwm_Op:
|
|
488
|
+ for(i=0; i<stack_idx; ++i)
|
|
489
|
+ ctl_regs[ kPwm_Enable_idx + i ] = stack[i];
|
|
490
|
+ pwm1_update();
|
|
491
|
+ break;
|
|
492
|
+
|
|
493
|
+ case kNoteOnUsec_Op:
|
|
494
|
+ for(i=0; i<stack_idx; ++i)
|
|
495
|
+ ctl_regs[ kTmr_Coarse_idx + i ] = stack[i];
|
|
496
|
+ tmr0_reset();
|
|
497
|
+ break;
|
458
|
498
|
|
459
|
|
- // ... otherwise this was a write request and the buffer
|
460
|
|
- // pointer is now pointing to the first byte to write to
|
461
|
|
- while(byteN--)
|
462
|
|
- {
|
463
|
|
- // write the value
|
464
|
|
- ctl_regs[reg_position] = usiTwiReceiveByte();
|
465
|
|
-
|
466
|
|
- // Set timer 1
|
467
|
|
- if( kTmr0_Prescale_idx <= reg_position && reg_position <= kTmr0_Fine_idx )
|
468
|
|
- { timer0_init(); }
|
469
|
|
- else
|
470
|
|
-
|
471
|
|
-
|
472
|
|
- // Set PWM 0
|
473
|
|
- if( kPWM0_Duty_idx <= reg_position && reg_position <= kPWM0_Freq_idx )
|
474
|
|
- { pwm0_update(); }
|
475
|
|
- else
|
476
|
|
-
|
477
|
|
- // Set timer 1
|
478
|
|
- if( kCS13_10_idx <= reg_position && reg_position <= kTmr1_Fine_idx )
|
479
|
|
- { timer1_init(); }
|
480
|
|
- else
|
481
|
|
-
|
482
|
|
- // Set PWM 1
|
483
|
|
- if( kPWM1_Duty_idx <= reg_position && reg_position <= kPWM1_Freq_idx )
|
484
|
|
- { pwm1_update(); }
|
485
|
|
- else
|
486
|
|
-
|
487
|
|
-
|
488
|
|
- // Write table
|
489
|
|
- if( reg_position == kTable_Fine_idx )
|
490
|
|
- { table_write_cur_value(); }
|
491
|
|
-
|
492
|
|
- reg_position++;
|
493
|
|
-
|
494
|
|
- if (reg_position >= reg_size)
|
|
499
|
+ case kNoteOff_Op:
|
|
500
|
+ TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // PWM interupt disable interrupts
|
|
501
|
+ PORTB &= ~_BV(HOLD_PIN); // clear the HOLD pin
|
|
502
|
+ break;
|
|
503
|
+
|
|
504
|
+
|
|
505
|
+ case kRead_Op:
|
|
506
|
+ if( stack_idx > 0 )
|
495
|
507
|
{
|
496
|
|
- reg_position = 0;
|
|
508
|
+ ctl_regs[ kRead_Src_idx ] = stack[0];
|
|
509
|
+
|
|
510
|
+ if( stack_idx > 1 )
|
|
511
|
+ ctl_regs[ ctl_regs[ kRead_Src_idx ] ] = stack[1];
|
497
|
512
|
}
|
|
513
|
+ break;
|
498
|
514
|
|
499
|
|
-
|
500
|
|
- }
|
501
|
|
-
|
502
|
|
-
|
|
515
|
+ case kWrite_Op:
|
|
516
|
+ _write_op( stack, stack_idx );
|
|
517
|
+ break;
|
|
518
|
+ }
|
503
|
519
|
}
|
504
|
520
|
|
505
|
521
|
|
506
|
|
-
|
507
|
522
|
int main(void)
|
508
|
523
|
{
|
509
|
524
|
cli(); // mask all interupts
|
510
|
525
|
|
511
|
526
|
|
512
|
|
- restore_memory_from_eeprom();
|
513
|
|
-
|
514
|
|
- DDRB |= _BV(DDB4) + _BV(DDB3) + _BV(DDB1); // setup PB4,PB3,PB1 as output
|
515
|
|
- PORTB &= ~(_BV(PINB4) + _BV(PINB3) + _BV(PINB1)); // clear output pins
|
|
527
|
+ DDRB |= _BV(ATTK_DIR) + _BV(HOLD_DIR) + _BV(LED_DIR); // setup PB4,PB3,PB1 as output
|
|
528
|
+ PORTB &= ~(_BV(ATTK_PIN) + _BV(HOLD_PIN) + _BV(LED_PIN)); // clear output pins
|
516
|
529
|
|
517
|
530
|
|
518
|
531
|
timer0_init();
|
|
@@ -525,9 +538,9 @@ int main(void)
|
525
|
538
|
|
526
|
539
|
sei();
|
527
|
540
|
|
528
|
|
- PINB = _BV(PINB4); // writes to PINB toggle the pins
|
|
541
|
+ PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
529
|
542
|
_delay_ms(1000);
|
530
|
|
- PINB = _BV(PINB4); // writes to PINB toggle the pins
|
|
543
|
+ PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
531
|
544
|
|
532
|
545
|
|
533
|
546
|
while(1)
|