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@@ -1,3 +1,15 @@
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+/*
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+ AT TINY 85
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+ +--\/--+
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+ RESET _| 1 8 |_ +5V
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+ ~OC1B HOLD DDB3 _| 2 7 |_ SCL
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+ OC1B ONSET DDB4 _| 3 6 |_ DDB1 LED
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+ GND _| 4 5 |_ SDA
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+ +------+
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+ * = Serial and/or programming pins on Arduino as ISP
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+*/
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+
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+
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// This program acts as the device (slave) for the control program i2c/a2a/c_ctl
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#define F_CPU 8000000L
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#include <stdio.h>
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@@ -7,123 +19,397 @@
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#include "usiTwiSlave.h"
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+
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#define I2C_SLAVE_ADDRESS 0x8 // the 7-bit address (remember to change this when adapting this example)
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enum
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{
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- kCS13_10_idx = 0, // Timer 1 Prescalar (CS13,CS12,CS11,CS10) from Table 12-5 pg 89 (0-15) prescaler = pow(2,val-1), 0=stop,1=1,2=2,3=4,4=8,....14=8192,15=16384 pre_scaled_hz = clock_hz/value
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- kTmr0_Coarse_idx = 1, // count of times timer0 count to 255 before OCR1C is set to Tmr0_Fine
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- kTmr0_Fine_idx = 2, // OCR1C timer match value
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- kPWM_Duty_idx = 3, //
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- kPWM_Freq_idx = 4, // 1-4 = clock divider=1=1,2=8,3=64,4=256,5=1024
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+ kTmr0_Prescale_idx = 0, // Timer 0 clock divider: 1=1,2=8,3=64,4=256,5=1024
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+ kTmr0_Coarse_idx = 1, //
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+ kTmr0_Fine_idx = 2, //
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+ kPWM0_Duty_idx = 3, //
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+ kPWM0_Freq_idx = 4, // 1-4 = clock divider=1=1,2=8,3=64,4=256,5=1024
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+ kCS13_10_idx = 5, // Timer 1 Prescalar (CS13,CS12,CS11,CS10) from Table 12-5 pg 89 (0-15) prescaler = pow(2,val-1), 0=stop,1=1,2=2,3=4,4=8,....14=8192,15=16384 pre_scaled_hz = clock_hz/value
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+ kTmr1_Coarse_idx = 6, // count of times timer0 count to 255 before OCR1C is set to Tmr0_Fine
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+ kTmr1_Fine_idx = 7, // OCR1C timer match value
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+ kPWM1_Duty_idx = 8, //
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+ kPWM1_Freq_idx = 9, //
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+ kTable_Addr_idx = 10, // Next table address to read/write
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+ kTable_Coarse_idx = 11, // Next table coarse value to read/write
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+ kTable_Fine_idx = 12, // Next table fine value to read/write
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+ kMax_idx
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};
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+
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volatile uint8_t ctl_regs[] =
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{
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- 9, // 0 9=32 us period w/ 8Mhz clock (timer tick rate)
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- 123, // 1 (0-255) Tmr0_Coarse count of times timer count to 255 before loading Tmr0_Minor for final count.
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- 8, // 2 (0-254) Tmr0_Fine OCR1C value on final phase before triggering timer
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- 127, // 3 (0-255) Duty cycle
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- 4, // 4 (1-4) PWM Frequency (clock pre-scaler)
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+ 4, // 0 (1-5) 4=32us per tick
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+ 123, // 1 (0-255) Timer 0 Coarse Value
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+ 8, // 2 (0-255) Timer 0 Fine Value
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+ 127, // 3 (0-255) Duty cycle
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+ 4, // 4 (1-4) PWM Frequency (clock pre-scaler)
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+ 9, // 5 9=32 us period w/ 8Mhz clock (timer tick rate)
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+ 123, // 6 (0-255) Tmr1_Coarse count of times timer count to 255 before loading Tmr0_Minor for final count.
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+ 8, // 7 (0-254) Tmr1_Fine OCR1C value on final phase before triggering timer
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+ 127, // 8 (0-255) PWM1 Duty cycle
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+ 254, // 9 (0-255) PWM1 Frequency (123 hz)
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+ 0, // 10 (0-127) Next table addr to read/write
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+ 0, // 11 (0-255) Next table coarse value to write
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+ 0, // 12 (0-255) Next table fine value to write
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};
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-// Tracks the current register pointer position
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-volatile uint8_t reg_position = 0;
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-const uint8_t reg_size = sizeof(ctl_regs);
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+#define tableN 256
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+uint8_t table[ tableN ];
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+
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// EEPROM
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+//
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+
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+void EEPROM_write(uint8_t ucAddress, uint8_t ucData)
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+{
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+ // Wait for completion of previous write
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+ while(EECR & (1<<EEPE))
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+ {}
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+
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+ EECR = (0<<EEPM1)|(0<<EEPM0); // Set Programming mode
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+ EEAR = ucAddress; // Set up address and data registers
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+ EEDR = ucData;
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+ EECR |= (1<<EEMPE); // Write logical one to EEMPE
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+ EECR |= (1<<EEPE); // Start eeprom write by setting EEPE
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+}
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+
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+
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+uint8_t EEPROM_read(uint8_t ucAddress)
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+{
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+ // Wait for completion of previous write
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+ while(EECR & (1<<EEPE))
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+ {}
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+
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+ EEAR = ucAddress; // Set up address register
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+ EECR |= (1<<EERE); // Start eeprom read by writing EERE
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+ return EEDR; // Return data from data register
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+}
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// Read/Write table
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+//
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+
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+// To write table value 42 to 127 (coarse) 64 (fine)
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+//
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+// w 8 kTable_Addr_idx 42
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+// w 8 kTable_Coarse_idx 127
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+// w 8 kTable_fine_idx 64
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+//
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+// TO read table value 42
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+// w 8 kTable_Addr_idx 42
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+// r 8 kTable_Coarse_idx -> 127
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+// r 8 kTable_Fine_idx -> 64
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+
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+
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+#define eeprom_addr( addr ) (kMax_idx + (addr))
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+
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+void table_write_cur_value( void )
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+{
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+ uint8_t tbl_addr = ctl_regs[ kTable_Addr_idx ] * 2;
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+
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+ table[ tbl_addr+0 ] = ctl_regs[ kTable_Coarse_idx ];
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+ table[ tbl_addr+1 ] = ctl_regs[ kTable_Fine_idx ];
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+
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+ EEPROM_write( eeprom_addr( tbl_addr+0 ), ctl_regs[ kTable_Coarse_idx ] );
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+ EEPROM_write( eeprom_addr( tbl_addr+1 ), ctl_regs[ kTable_Fine_idx ]);
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+}
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+
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+void table_load( void )
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+{
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+ uint8_t i = 0;
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+
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+ for(; i<128; ++i)
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+ {
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+ uint8_t tbl_addr = i*2;
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+ table[tbl_addr+0] = EEPROM_read( eeprom_addr(tbl_addr+0) );
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+ table[tbl_addr+1] = EEPROM_read( eeprom_addr(tbl_addr+1) );
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+ }
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+}
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+
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+void restore_memory_from_eeprom( void )
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+{
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+ /*
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+ uint8_t i;
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+ for(i=0; i<kMax_idx; ++i)
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+ {
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+ ctl_regs[i] = EEPROM_read( eeprom_addr( i ) );
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+ }
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+ */
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+
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+ table_load();
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+}
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+
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// Timer0
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+//
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-volatile uint8_t tmr_state = 0;
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-volatile uint8_t tmr_coarse_cur = 0;
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+volatile uint8_t tmr0_state = 0; // 0=disabled 1=coarse mode, 2=fine mode
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+volatile uint8_t tmr0_coarse_cur = 0;
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-void tmr_reset()
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+// Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
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+void tmr0_reset()
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{
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+ // if a coarse count exists then go into coarse mode
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if( ctl_regs[kTmr0_Coarse_idx] > 0 )
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{
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- tmr_state = 1;
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- OCR1C = 254;
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+ tmr0_state = 1;
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+ OCR0A = 0xff;
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}
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- else
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+ else // otherwise go into fine mode
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{
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- tmr_state = 2;
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- OCR1C = ctl_regs[kTmr0_Fine_idx];
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+ tmr0_state = 2;
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+ OCR0A = ctl_regs[kTmr0_Fine_idx];
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}
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180
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- tmr_coarse_cur = 0;
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+ tmr0_coarse_cur = 0;
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}
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-ISR(TIMER1_OVF_vect)
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+ISR(TIMER0_COMPA_vect)
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{
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- switch( tmr_state )
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+ switch( tmr0_state )
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{
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case 0:
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+ // disabled
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break;
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-
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- case 1:
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- if( ++tmr_coarse_cur >= ctl_regs[kTmr0_Coarse_idx] )
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+
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+ case 1:
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+ // coarse mode
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+ if( ++tmr0_coarse_cur >= ctl_regs[kTmr0_Coarse_idx] )
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{
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- tmr_state = 2;
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- OCR1C = ctl_regs[kTmr0_Fine_idx];
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+ tmr0_state = 2;
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+ OCR0A = ctl_regs[kTmr0_Fine_idx];
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}
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break;
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-
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+
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case 2:
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- PINB = _BV(PINB4) + _BV(PINB1); // writes to PINB toggle the pins
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+ // fine mode
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+ PINB = _BV(PINB4); // writes to PINB toggle the pins
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204
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- tmr_reset();
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+ tmr0_reset(); // restart the timer
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break;
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}
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-
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-
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}
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-void timer1_init()
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+void timer0_init()
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{
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- TIMSK &= ~_BV(TOIE1); // Disable interrupt TIMER1_OVF
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- OCR1A = 255; // Set to anything greater than OCR1C (the counter never gets here.)
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- TCCR1 |= _BV(CTC1); // Reset TCNT1 to 0 when TCNT1==OCR1C
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- TCCR1 |= _BV(PWM1A); // Enable PWM A
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- TCCR1 |= ctl_regs[kCS13_10_idx] & 0x0f; //
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- GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
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+ TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
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+ TCCR0A |= 0x02; // CTC mode
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+ TCCR0B |= ctl_regs[kTmr0_Prescale_idx]; // set the prescaler
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216
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- tmr_reset();
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+ GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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- TIMSK |= _BV(TOIE1); // Enable interrupt TIMER1_OVF
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+ tmr0_reset(); // set the timers starting state
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220
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+ TIMSK |= _BV(OCIE0A); // Enable interrupt TIMER1_OVF
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+
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}
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// PWM (Timer0)
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+//
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+
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void pwm0_update()
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{
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- OCR0B = ctl_regs[kPWM_Duty_idx]; // 50% duty cycle
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- TCCR0B |= ctl_regs[kPWM_Freq_idx]; // PWM frequency pre-scaler
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+ OCR0B = ctl_regs[kPWM0_Duty_idx]; // 50% duty cycle
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+ TCCR0B |= ctl_regs[kPWM0_Freq_idx]; // PWM frequency pre-scaler
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}
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238
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void pwm0_init()
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240
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{
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- //WGM[1:0] = 3 (TOP=255)
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+ // WGM[1:0] = 3 (TOP=255)
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// OCR0B = duty cycle (0-100%)
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// COM0A[1:0] = 2 non-inverted
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//
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245
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108
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TCCR0A |= 0x20 + 3; // 0x20=non-inverting 3=WGM bits Fast-PWM mode (0=Bot 255=Top)
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TCCR0B |= 0x00 + 4; // 3=256 pre-scaler 122Hz=1Mghz/(v*256) where v=64
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+
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+ GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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250
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111
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pwm0_update();
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+
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+
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254
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+ DDRB |= _BV(DDB1); // set direction on
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255
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+}
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+
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+
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+
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//------------------------------------------------------------------------------
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+//
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+// Timer1
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+//
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+
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+volatile uint8_t tmr1_state = 0;
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+volatile uint8_t tmr1_coarse_cur = 0;
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268
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+static uint8_t tmr1_init_fl = 0;
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+
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270
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+void tmr1_reset()
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+{
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272
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+ if( ctl_regs[kTmr1_Coarse_idx] > 0 )
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+ {
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+ tmr1_state = 1;
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+ OCR1C = 254;
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+ }
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+ else
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+ {
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279
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+ tmr1_state = 2;
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280
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+ OCR1C = ctl_regs[kTmr1_Fine_idx];
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281
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+ }
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282
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+
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+ tmr1_coarse_cur = 0;
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+}
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285
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+
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286
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+ISR(TIMER1_OVF_vect)
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287
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+{
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288
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+ if( !tmr1_init_fl )
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+ {
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290
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+ PORTB |= _BV(PINB3); // set PWM pin
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291
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+ }
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292
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+ else
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293
|
+ {
|
|
294
|
+ switch( tmr1_state )
|
|
295
|
+ {
|
112
|
296
|
|
113
|
|
- DDRB |= _BV(DDB1);
|
|
297
|
+ case 0:
|
|
298
|
+ // disabled
|
|
299
|
+ break;
|
|
300
|
+
|
|
301
|
+ case 1:
|
|
302
|
+ // coarse mode
|
|
303
|
+ if( ++tmr1_coarse_cur >= ctl_regs[kTmr1_Coarse_idx] )
|
|
304
|
+ {
|
|
305
|
+ tmr1_state = 2;
|
|
306
|
+ OCR1C = ctl_regs[kTmr1_Fine_idx];
|
|
307
|
+ }
|
|
308
|
+ break;
|
|
309
|
+
|
|
310
|
+ case 2:
|
|
311
|
+ // fine mode
|
|
312
|
+ PINB = _BV(PINB4); // writes to PINB toggle the pins
|
|
313
|
+
|
|
314
|
+ tmr1_reset();
|
|
315
|
+ break;
|
|
316
|
+ }
|
|
317
|
+ }
|
114
|
318
|
}
|
115
|
319
|
|
|
320
|
+void timer1_init()
|
|
321
|
+{
|
|
322
|
+ TIMSK &= ~_BV(TOIE1); // Disable interrupt TIMER1_OVF
|
|
323
|
+ OCR1A = 255; // Set to anything greater than OCR1C (the counter never gets here.)
|
|
324
|
+ TCCR1 |= _BV(CTC1); // Reset TCNT1 to 0 when TCNT1==OCR1C
|
|
325
|
+ TCCR1 |= _BV(PWM1A); // Enable PWM A (to generate overflow interrupts)
|
|
326
|
+ TCCR1 |= ctl_regs[kCS13_10_idx] & 0x0f; //
|
|
327
|
+ GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
|
|
328
|
+
|
|
329
|
+ tmr1_reset();
|
|
330
|
+ tmr1_init_fl = 1;
|
|
331
|
+ TIMSK |= _BV(TOIE1); // Enable interrupt TIMER1_OVF
|
|
332
|
+}
|
116
|
333
|
|
117
|
|
-/**
|
118
|
|
- * This is called for each read request we receive, never put more
|
119
|
|
- * than one byte of data (with TinyWireS.send) to the send-buffer when
|
120
|
|
- * using this callback
|
121
|
|
- */
|
|
334
|
+//------------------------------------------------------------------------------
|
|
335
|
+//------------------------------------------------------------------------------
|
|
336
|
+//------------------------------------------------------------------------------
|
|
337
|
+//
|
|
338
|
+// PWM1
|
|
339
|
+//
|
|
340
|
+// PWM is optimized to use pins OC1A ,~OC1A, OC1B, ~OC1B but this code
|
|
341
|
+// but since these pins are not available this code uses
|
|
342
|
+// ISR's to redirect the output to PIN3
|
|
343
|
+
|
|
344
|
+void pwm1_update()
|
|
345
|
+{
|
|
346
|
+ OCR1B = ctl_regs[kPWM1_Duty_idx]; // control duty cycle
|
|
347
|
+ OCR1C = ctl_regs[kPWM1_Freq_idx]; // PWM frequency pre-scaler
|
|
348
|
+}
|
|
349
|
+
|
|
350
|
+ISR(TIMER1_COMPB_vect)
|
|
351
|
+{
|
|
352
|
+ PORTB &= ~(_BV(PINB3)); // clear PWM pin
|
|
353
|
+}
|
|
354
|
+
|
|
355
|
+
|
|
356
|
+void pwm1_init()
|
|
357
|
+{
|
|
358
|
+ TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // Disable interrupts
|
|
359
|
+
|
|
360
|
+ DDRB |= _BV(DDB3); // setup PB3 as output
|
|
361
|
+
|
|
362
|
+ // set on TCNT1 == 0 // happens when TCNT1 matches OCR1C
|
|
363
|
+ // clr on OCR1B == TCNT // happens when TCNT1 matches OCR1B
|
|
364
|
+ // // COM1B1=1 COM1B0=0 (enable output on ~OC1B)
|
|
365
|
+ TCCR1 |= 9; // 32us period (256 divider) prescaler
|
|
366
|
+ GTCCR |= _BV(PWM1B); // Enable PWM B and disconnect output pins
|
|
367
|
+ GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
|
|
368
|
+
|
|
369
|
+ pwm1_update();
|
|
370
|
+
|
|
371
|
+ TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // Enable interrupts
|
|
372
|
+
|
|
373
|
+
|
|
374
|
+
|
|
375
|
+}
|
|
376
|
+
|
|
377
|
+//------------------------------------------------------------------------------
|
|
378
|
+//------------------------------------------------------------------------------
|
|
379
|
+//------------------------------------------------------------------------------
|
|
380
|
+
|
|
381
|
+// Tracks the current register pointer position
|
|
382
|
+volatile uint8_t reg_position = 0;
|
|
383
|
+const uint8_t reg_size = sizeof(ctl_regs);
|
|
384
|
+
|
|
385
|
+//
|
|
386
|
+// Read Request Handler
|
|
387
|
+//
|
|
388
|
+// This is called for each read request we receive, never put more
|
|
389
|
+// than one byte of data (with TinyWireS.send) to the send-buffer when
|
|
390
|
+// using this callback
|
|
391
|
+//
|
122
|
392
|
void on_request()
|
123
|
393
|
{
|
124
|
|
- // read and transmit the requestd position
|
125
|
|
- usiTwiTransmitByte(ctl_regs[reg_position]);
|
|
394
|
+ uint8_t val = 0;
|
|
395
|
+
|
|
396
|
+ switch( reg_position )
|
|
397
|
+ {
|
|
398
|
+ case kTable_Coarse_idx:
|
|
399
|
+ val = table[ ctl_regs[kTable_Addr_idx]*2 + 0 ];
|
|
400
|
+ break;
|
|
401
|
+
|
|
402
|
+ case kTable_Fine_idx:
|
|
403
|
+ val = table[ ctl_regs[kTable_Addr_idx]*2 + 1 ];
|
|
404
|
+ break;
|
|
405
|
+
|
|
406
|
+ default:
|
|
407
|
+ // read and transmit the requestd position
|
|
408
|
+ val = ctl_regs[reg_position];
|
126
|
409
|
|
|
410
|
+ }
|
|
411
|
+
|
|
412
|
+ usiTwiTransmitByte(val);
|
127
|
413
|
|
128
|
414
|
// Increment the reg position on each read, and loop back to zero
|
129
|
415
|
reg_position++;
|
|
@@ -135,14 +421,14 @@ void on_request()
|
135
|
421
|
}
|
136
|
422
|
|
137
|
423
|
|
138
|
|
-/**
|
139
|
|
- * The I2C data received -handler
|
140
|
|
- *
|
141
|
|
- * This needs to complete before the next incoming transaction (start,
|
142
|
|
- * data, restart/stop) on the bus does so be quick, set flags for long
|
143
|
|
- * running tasks to be called from the mainloop instead of running
|
144
|
|
- * them directly,
|
145
|
|
- */
|
|
424
|
+//
|
|
425
|
+// The I2C data received -handler
|
|
426
|
+//
|
|
427
|
+// This needs to complete before the next incoming transaction (start,
|
|
428
|
+// data, restart/stop) on the bus does so be quick, set flags for long
|
|
429
|
+// running tasks to be called from the mainloop instead of running
|
|
430
|
+// them directly,
|
|
431
|
+//
|
146
|
432
|
|
147
|
433
|
void on_receive( uint8_t byteN )
|
148
|
434
|
{
|
|
@@ -174,21 +460,45 @@ void on_receive( uint8_t byteN )
|
174
|
460
|
// pointer is now pointing to the first byte to write to
|
175
|
461
|
while(byteN--)
|
176
|
462
|
{
|
177
|
|
- ctl_regs[reg_position] = usiTwiReceiveByte();
|
178
|
|
-
|
179
|
|
- if( kCS13_10_idx <= reg_position && reg_position <= kTmr0_Fine_idx )
|
180
|
|
- timer1_init();
|
|
463
|
+ // write the value
|
|
464
|
+ ctl_regs[reg_position] = usiTwiReceiveByte();
|
|
465
|
+
|
|
466
|
+ // Set timer 1
|
|
467
|
+ if( kTmr0_Prescale_idx <= reg_position && reg_position <= kTmr0_Fine_idx )
|
|
468
|
+ { timer0_init(); }
|
|
469
|
+ else
|
|
470
|
+
|
|
471
|
+
|
|
472
|
+ // Set PWM 0
|
|
473
|
+ if( kPWM0_Duty_idx <= reg_position && reg_position <= kPWM0_Freq_idx )
|
|
474
|
+ { pwm0_update(); }
|
181
|
475
|
else
|
182
|
|
- if( kPWM_Duty_idx <= reg_position && reg_position <= kPWM_Freq_idx )
|
183
|
|
- pwm0_update();
|
|
476
|
+
|
|
477
|
+ // Set timer 1
|
|
478
|
+ if( kCS13_10_idx <= reg_position && reg_position <= kTmr1_Fine_idx )
|
|
479
|
+ { timer1_init(); }
|
|
480
|
+ else
|
|
481
|
+
|
|
482
|
+ // Set PWM 1
|
|
483
|
+ if( kPWM1_Duty_idx <= reg_position && reg_position <= kPWM1_Freq_idx )
|
|
484
|
+ { pwm1_update(); }
|
|
485
|
+ else
|
|
486
|
+
|
|
487
|
+
|
|
488
|
+ // Write table
|
|
489
|
+ if( reg_position == kTable_Fine_idx )
|
|
490
|
+ { table_write_cur_value(); }
|
|
491
|
+
|
|
492
|
+ reg_position++;
|
|
493
|
+
|
|
494
|
+ if (reg_position >= reg_size)
|
|
495
|
+ {
|
|
496
|
+ reg_position = 0;
|
|
497
|
+ }
|
184
|
498
|
|
185
|
499
|
|
186
|
|
- reg_position++;
|
187
|
|
- if (reg_position >= reg_size)
|
188
|
|
- {
|
189
|
|
- reg_position = 0;
|
190
|
|
- }
|
191
|
500
|
}
|
|
501
|
+
|
192
|
502
|
|
193
|
503
|
}
|
194
|
504
|
|
|
@@ -197,16 +507,20 @@ void on_receive( uint8_t byteN )
|
197
|
507
|
int main(void)
|
198
|
508
|
{
|
199
|
509
|
cli(); // mask all interupts
|
200
|
|
-
|
201
|
|
- DDRB |= _BV(DDB4) + _BV(DDB1); // setup PB4 as output
|
202
|
|
- PORTB &= ~(_BV(PINB4) + _BV(PINB1));
|
203
|
510
|
|
204
|
|
- timer1_init();
|
205
|
|
- pwm0_init();
|
|
511
|
+
|
|
512
|
+ restore_memory_from_eeprom();
|
|
513
|
+
|
|
514
|
+ DDRB |= _BV(DDB4) + _BV(DDB3) + _BV(DDB1); // setup PB4,PB3,PB1 as output
|
|
515
|
+ PORTB &= ~(_BV(PINB4) + _BV(PINB3) + _BV(PINB1)); // clear output pins
|
|
516
|
+
|
|
517
|
+
|
|
518
|
+ timer0_init();
|
|
519
|
+ pwm1_init();
|
206
|
520
|
|
207
|
521
|
// setup i2c library
|
208
|
|
- usi_onReceiverPtr = on_receive; //on_receive;
|
209
|
|
- usi_onRequestPtr = on_request;
|
|
522
|
+ usi_onReceiverPtr = on_receive;
|
|
523
|
+ usi_onRequestPtr = on_request;
|
210
|
524
|
usiTwiSlaveInit(I2C_SLAVE_ADDRESS);
|
211
|
525
|
|
212
|
526
|
sei();
|