Picadae hardware and control code
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i2c_timer_pwm_3.c 16KB

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  1. //| Copyright: (C) 2018-2020 Kevin Larke <contact AT larke DOT org>
  2. //| License: GNU GPL version 3.0 or above. See the accompanying LICENSE file.
  3. // w 60 0 1 10 : w i2c_addr SetPWM enable duty_val
  4. // w 60 5 12 8 32 : w i2c_addr write addrFl|src coarse_val
  5. // w 60 4 0 5 : w i2c_addr read src read_addr (set the read address to register 5)
  6. // r 60 4 3 : r i2c_addr <dum> cnt (read the first 3 reg's beginning w/ 5)
  7. /*
  8. AT TINY 85
  9. +--\/--+
  10. RESET _| 1 8 |_ +5V
  11. ~OC1B HOLD DDB3 _| 2 7 |_ SCL yellow
  12. OC1B ONSET DDB4 _| 3 6 |_ DDB1 LED
  13. GND _| 4 5 |_ SDA orange
  14. +------+
  15. * = Serial and/or programming pins on Arduino as ISP
  16. */
  17. // This program acts as the device (slave) for the control program i2c/a2a/c_ctl
  18. #define F_CPU 16000000L
  19. #include <stdio.h>
  20. #include <avr/io.h>
  21. #include <util/delay.h>
  22. #include <avr/interrupt.h>
  23. #include "usiTwiSlave.h"
  24. #define HOLD_DIR DDB3
  25. #define ATTK_DIR DDB4
  26. #define LED_DIR DDB1
  27. #define HOLD_PIN PINB3
  28. #define ATTK_PIN PINB4
  29. #define LED_PIN PINB1
  30. // Opcodes
  31. enum
  32. {
  33. kSetPwm_Op = 0, // Set PWM duty/hz/div 0 {<duty> {<freq> {<div>}}} div:2=2,3=4,4=8,5=16,6=32,7=64,8=128,9=256,10=512,11=1024,12=2048,13=4096,14=8192,15=16384
  34. kNoteOnVel_Op = 1, // Turn on note 3 {<vel>}
  35. kNoteOnUsec_Op = 2, // Turn on note 4 {<coarse> {<fine> {<prescale>}}}
  36. kNoteOff_Op = 3, // Turn off note 5
  37. kSetReadAddr_Op = 4, // Set a read addr. 6 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
  38. kWrite_Op = 5, // Set write 7 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
  39. kSetMode_Op = 6, // Set the mode flags 8 {<mode>} 1=repeat 2=pwm
  40. kWriteTable_Op = 7, // Write table to EEprom 9
  41. kInvalid_Op = 8 //
  42. };
  43. enum
  44. {
  45. kReg_Rd_Addr_idx = 0, // Next Reg Address to read
  46. kTable_Rd_Addr_idx = 1, // Next Table Address to read
  47. kEE_Rd_Addr_idx = 2, // Next EEPROM address to read
  48. kRead_Src_idx = 3, // kReg_Rd_Addr_idx=reg, kTable_Rd_Addr_idx=table, kEE_Rd_Addr_idx=eeprom
  49. kReg_Wr_Addr_idx = 4, // Next Reg Address to write
  50. kTable_Wr_Addr_idx = 5, // Next Table Address to write
  51. kEE_Wr_Addr_idx = 6, // Next EEPROM address to write
  52. kWrite_Dst_idx = 7, // kReg_Wr_Addr_idx=reg, kTable_Wr_Addr_idx=table, kEE_Wr_Addr_idx=eeprom
  53. kTmr_Coarse_idx = 8, //
  54. kTmr_Fine_idx = 9, //
  55. kTmr_Prescale_idx = 10, // Timer 0 clock divider: 1=1,2=8,3=64,4=256,5=1024 Default: 4 (16us)
  56. kPwm_Duty_idx = 11, //
  57. kPwm_Freq_idx = 12, //
  58. kPwm_Div_idx = 13, //
  59. kMode_idx = 14, // 1=repeat 2=pwm
  60. kState_idx = 15, // 1=attk 2=hold
  61. kError_Code_idx = 16, // Error Code
  62. kMax_idx
  63. };
  64. enum
  65. {
  66. kMode_Repeat_Fl = 1,
  67. kMode_Pwm_Fl = 2,
  68. kState_Attk_Fl = 1,
  69. kState_Hold_Fl = 2
  70. };
  71. #define isInRepeatMode() ctl_regs[ kMode_idx ] & kMode_Repeat_Fl
  72. #define isInPwmMode() ctl_regs[ kMode_idx ] & kMode_Pwm_Fl
  73. // Flags:
  74. // 1=Repeat: 1=Timer and PWM are free running. This allows testing with LED's. 0=Timer triggers does not reset on time out.
  75. // 2=PWM: On timer timeout 1=PWM HOLD 0=Set HOLD
  76. volatile uint8_t ctl_regs[] =
  77. {
  78. 0, // 0 (0-(kMax_idx-1)) Reg Read Addr
  79. 0, // 1 (0-255) Table Read Addr
  80. 0, // 2 (0-255) EE Read Addr
  81. kReg_Rd_Addr_idx, // 3 (0-2) Read source
  82. 0, // 4 (0-(kMax_idx-1)) Reg Write Addr
  83. 0, // 5 (0-255) Table Write Addr
  84. 0, // 6 (0-255) EE Write Addr
  85. kReg_Wr_Addr_idx, // 7 (0-2) Write source
  86. 245, // 8 (0-255) Timer 0 Coarse Value
  87. 25, // 9 (0-255) Timer 0 Fine Value
  88. 4, // 10 (1-5) 4=16us per tick
  89. 127, // 11 (0-255) Pwm Duty cycle
  90. 254, // 12 (0-255) Pwm Frequency (123 Hz)
  91. 10, // 13 (0-15) Pwm clock div
  92. kMode_Repeat_Fl, // 14 mode flags 1=Repeat 2=PWM
  93. 0, // 15 state flags 1=attk 2=hold (read/only)
  94. 0, // 16 (0-255) Error bit field
  95. };
  96. // These registers are saved to Eeprom
  97. uint8_t eeprom_addr[] =
  98. {
  99. kTmr_Prescale_idx,
  100. kPwm_Duty_idx,
  101. kPwm_Freq_idx,
  102. kPwm_Div_idx
  103. };
  104. #define tableN 256
  105. uint8_t table[ tableN ]; // [ coarse_0,fine_0, coarse_1, fine_1, .... coarse_127,fine_127]
  106. enum
  107. {
  108. kInvalid_Read_Src_ErrFl = 0x01,
  109. kInvalid_Write_Dst_ErrFl = 0x02
  110. };
  111. #define set_error( flag ) ctl_regs[ kError_Code_idx ] |= (flag)
  112. //------------------------------------------------------------------------------
  113. //------------------------------------------------------------------------------
  114. //------------------------------------------------------------------------------
  115. //
  116. // EEPROM
  117. //
  118. void EEPROM_write(uint8_t ucAddress, uint8_t ucData)
  119. {
  120. // Wait for completion of previous write
  121. while(EECR & (1<<EEPE))
  122. {}
  123. EECR = (0<<EEPM1)|(0<<EEPM0); // Set Programming mode
  124. EEAR = ucAddress; // Set up address and data registers
  125. EEDR = ucData;
  126. EECR |= (1<<EEMPE); // Write logical one to EEMPE
  127. EECR |= (1<<EEPE); // Start eeprom write by setting EEPE
  128. }
  129. uint8_t EEPROM_read(uint8_t ucAddress)
  130. {
  131. // Wait for completion of previous write
  132. while(EECR & (1<<EEPE))
  133. {}
  134. EEAR = ucAddress; // Set up address register
  135. EECR |= (1<<EERE); // Start eeprom read by writing EERE
  136. return EEDR; // Return data from data register
  137. }
  138. void write_table()
  139. {
  140. uint8_t i;
  141. uint8_t regN = sizeof(eeprom_addr);
  142. // write the persistent registers
  143. for(i=0; i<regN; ++i)
  144. EEPROM_write( i, ctl_regs[ eeprom_addr[i] ] );
  145. // write the table
  146. for(i=0; i<tableN; ++i)
  147. EEPROM_write( regN+i, table[i] );
  148. }
  149. void load_table()
  150. {
  151. uint8_t i;
  152. uint8_t regN = sizeof(eeprom_addr);
  153. // read the persistent registers
  154. for(i=0; i<regN; ++i)
  155. ctl_regs[ eeprom_addr[i] ] = EEPROM_read(i);
  156. // read the tabke
  157. for(i=0; i<tableN; ++i)
  158. table[i] = EEPROM_read(regN + i);
  159. }
  160. //------------------------------------------------------------------------------
  161. //------------------------------------------------------------------------------
  162. //------------------------------------------------------------------------------
  163. //
  164. // Timer0
  165. //
  166. volatile uint8_t tmr0_state = 0; // current timer mode: 0=disabled 1=coarse mode, 2=fine mode
  167. volatile uint8_t tmr0_coarse_cur = 0;
  168. #define set_attack() do { ctl_regs[kState_idx] |= kState_Attk_Fl; PORTB |= _BV(ATTK_PIN); } while(0)
  169. #define clear_attack() do { PORTB &= ~_BV(ATTK_PIN); ctl_regs[kState_idx] &= ~kState_Attk_Fl; } while(0)
  170. // Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
  171. void tmr0_reset()
  172. {
  173. tmr0_coarse_cur = 0; // clear the coarse time counter
  174. ctl_regs[kState_idx] |= kState_Attk_Fl; // set the attack state
  175. PORTB |= _BV(ATTK_PIN); // set the attack pin
  176. // if a coarse count exists then go into coarse mode
  177. if( ctl_regs[kTmr_Coarse_idx] > 0 )
  178. {
  179. tmr0_state = 1;
  180. OCR0A = 0xff;
  181. }
  182. else // otherwise go into fine mode
  183. {
  184. tmr0_state = 2;
  185. OCR0A = ctl_regs[kTmr_Fine_idx];
  186. }
  187. TIMSK |= _BV(OCIE0A); // enable the timer interrupt
  188. }
  189. ISR(TIMER0_COMPA_vect)
  190. {
  191. switch( tmr0_state )
  192. {
  193. case 0:
  194. // timer is disabled
  195. break;
  196. case 1:
  197. // coarse mode
  198. if( ++tmr0_coarse_cur >= ctl_regs[kTmr_Coarse_idx] )
  199. {
  200. tmr0_state = 2;
  201. OCR0A = ctl_regs[kTmr_Fine_idx];
  202. }
  203. break;
  204. case 2:
  205. // fine mode
  206. // This marks the end of a timer period
  207. // If in repeat mode ...
  208. if(ctl_regs[kMode_idx] & kMode_Repeat_Fl)
  209. {
  210. // store the current state of the attack flag
  211. uint8_t fl = ctl_regs[kState_idx] & kState_Attk_Fl;
  212. tmr0_reset(); // ... restart the timer
  213. // ATTK_PIN is always set after tmr0_reset() but we need to toggle in 'repeat' mode
  214. if( fl )
  215. {
  216. clear_attack();
  217. }
  218. // In repeat mode we always run the PWM output continuously.
  219. // This guarantees that no matter how the modes may be changing that PWM will be enabled.
  220. TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // Enable PWM interrupts
  221. }
  222. else // ... not in repeat mode
  223. {
  224. clear_attack();
  225. if( ctl_regs[kMode_idx] & kMode_Pwm_Fl)
  226. {
  227. TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // PWM interupt Enable interrupts
  228. }
  229. else
  230. {
  231. PORTB |= _BV(HOLD_PIN); // set the HOLD pin
  232. }
  233. TIMSK &= ~_BV(OCIE0A); // clear timer interrupt
  234. }
  235. break;
  236. }
  237. }
  238. void tmr0_init()
  239. {
  240. TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
  241. TCCR0A |= 0x02; // CTC mode
  242. TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
  243. GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
  244. }
  245. //------------------------------------------------------------------------------
  246. //------------------------------------------------------------------------------
  247. //------------------------------------------------------------------------------
  248. //
  249. // Pwm
  250. //
  251. // PWM is optimized to use pins OC1A ,~OC1A, OC1B, ~OC1B
  252. // but since these pins are not available this code uses
  253. // ISR's to redirect the output to PIN3
  254. void pwm1_update()
  255. {
  256. OCR1B = ctl_regs[kPwm_Duty_idx]; // control duty cycle
  257. OCR1C = ctl_regs[kPwm_Freq_idx]; // PWM frequency pre-scaler
  258. }
  259. ISR(TIMER1_OVF_vect)
  260. {
  261. PORTB |= _BV(HOLD_PIN); // set PWM pin
  262. }
  263. ISR(TIMER1_COMPB_vect)
  264. {
  265. PORTB &= ~(_BV(HOLD_PIN)); // clear PWM pin
  266. }
  267. void pwm1_init()
  268. {
  269. TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // Disable interrupts
  270. DDRB |= _BV(HOLD_DIR); // setup PB3 as output
  271. // set on TCNT1 == 0 // happens when TCNT1 matches OCR1C
  272. // clr on OCR1B == TCNT // happens when TCNT1 matches OCR1B
  273. // // COM1B1=1 COM1B0=0 (enable output on ~OC1B)
  274. TCCR1 |= ctl_regs[ kPwm_Div_idx]; // 32us period (512 divider) prescaler
  275. GTCCR |= _BV(PWM1B); // Enable PWM B and disconnect output pins
  276. GTCCR |= _BV(PSR1); // Set the pre-scaler to the selected value
  277. pwm1_update();
  278. }
  279. //------------------------------------------------------------------------------
  280. //------------------------------------------------------------------------------
  281. //------------------------------------------------------------------------------
  282. // Tracks the current register pointer position
  283. volatile uint8_t reg_position = 0;
  284. const uint8_t reg_size = sizeof(ctl_regs);
  285. //
  286. // Read Request Handler
  287. //
  288. // This is called for each read request we receive, never put more
  289. // than one byte of data (with TinyWireS.send) to the send-buffer when
  290. // using this callback
  291. //
  292. void on_request()
  293. {
  294. uint8_t val = 0;
  295. switch( ctl_regs[ kRead_Src_idx ] )
  296. {
  297. case kReg_Rd_Addr_idx:
  298. val = ctl_regs[ ctl_regs[kReg_Rd_Addr_idx] ];
  299. break;
  300. case kTable_Rd_Addr_idx:
  301. val = table[ ctl_regs[kTable_Rd_Addr_idx] ];
  302. break;
  303. case kEE_Rd_Addr_idx:
  304. val = EEPROM_read(ctl_regs[kEE_Rd_Addr_idx]);
  305. break;
  306. default:
  307. set_error( kInvalid_Read_Src_ErrFl );
  308. return;
  309. }
  310. usiTwiTransmitByte(val);
  311. ctl_regs[ ctl_regs[ kRead_Src_idx ] ] += 1;
  312. }
  313. void _write_op( uint8_t* stack, uint8_t stackN )
  314. {
  315. uint8_t stack_idx = 0;
  316. if( stackN > 0 )
  317. {
  318. uint8_t src = stack[0] & 0x07;
  319. uint8_t addr_fl = stack[0] & 0x08;
  320. // verify the source value
  321. if( src < kReg_Wr_Addr_idx || src > kEE_Wr_Addr_idx )
  322. {
  323. set_error( kInvalid_Write_Dst_ErrFl );
  324. return;
  325. }
  326. // set the write source
  327. stack_idx = 1;
  328. ctl_regs[ kWrite_Dst_idx ] = src;
  329. // if an address value was passed also ....
  330. if( addr_fl && stackN > 1 )
  331. {
  332. stack_idx = 2;
  333. ctl_regs[ src ] = stack[1];
  334. }
  335. }
  336. //
  337. for(; stack_idx<stackN; ++stack_idx)
  338. {
  339. uint8_t addr_idx = ctl_regs[ ctl_regs[kWrite_Dst_idx] ]++;
  340. uint8_t val = stack[ stack_idx ];
  341. switch( ctl_regs[ kWrite_Dst_idx ] )
  342. {
  343. case kReg_Wr_Addr_idx: ctl_regs[ addr_idx ] = val; break;
  344. case kTable_Wr_Addr_idx: table[ addr_idx ] = val; break;
  345. case kEE_Wr_Addr_idx: EEPROM_write( table[ addr_idx ], val); break;
  346. default:
  347. set_error( kInvalid_Write_Dst_ErrFl );
  348. break;
  349. }
  350. }
  351. }
  352. //
  353. // The I2C data received -handler
  354. //
  355. // This needs to complete before the next incoming transaction (start,
  356. // data, restart/stop) on the bus does so be quick, set flags for long
  357. // running tasks to be called from the mainloop instead of running
  358. // them directly,
  359. //
  360. void on_receive( uint8_t byteN )
  361. {
  362. PINB = _BV(LED_PIN); // writes to PINB toggle the pins
  363. const uint8_t stackN = 16;
  364. uint8_t stack_idx = 0;
  365. uint8_t stack[ stackN ];
  366. uint8_t i;
  367. if (byteN < 1 || byteN > TWI_RX_BUFFER_SIZE)
  368. {
  369. // Sanity-check
  370. return;
  371. }
  372. // get the register index to read/write
  373. uint8_t op_id = usiTwiReceiveByte();
  374. byteN--;
  375. // If only one byte was received then this was a read request
  376. // and the buffer pointer (reg_position) is now set to return the byte
  377. // at this location on the subsequent call to on_request() ...
  378. if(byteN)
  379. {
  380. while( byteN-- )
  381. {
  382. stack[stack_idx] = usiTwiReceiveByte();
  383. ++stack_idx;
  384. }
  385. }
  386. switch( op_id )
  387. {
  388. case kSetPwm_Op:
  389. for(i=0; i<stack_idx && i<3; ++i)
  390. ctl_regs[ kPwm_Duty_idx + i ] = stack[i];
  391. // if the PWM prescaler was changed
  392. if( i == 3 )
  393. pwm1_init();
  394. pwm1_update();
  395. break;
  396. case kNoteOnUsec_Op:
  397. for(i=0; i<stack_idx && i<3; ++i)
  398. ctl_regs[ kTmr_Coarse_idx + i ] = stack[i];
  399. // if a prescaler was included then the timer needs to be re-initialized
  400. if( i == 3 )
  401. tmr0_init();
  402. tmr0_reset();
  403. break;
  404. case kNoteOff_Op:
  405. TIMSK &= ~_BV(OCIE0A); // clear timer interrupt (shouldn't be necessary)
  406. TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // PWM interupt disable interrupts
  407. PORTB &= ~_BV(HOLD_PIN); // clear the HOLD pin
  408. break;
  409. case kSetReadAddr_Op:
  410. if( stack_idx > 0 )
  411. {
  412. ctl_regs[ kRead_Src_idx ] = stack[0];
  413. if( stack_idx > 1 )
  414. ctl_regs[ ctl_regs[ kRead_Src_idx ] ] = stack[1];
  415. }
  416. break;
  417. case kWrite_Op:
  418. _write_op( stack, stack_idx );
  419. break;
  420. case kSetMode_Op:
  421. if( stack_idx > 0)
  422. {
  423. ctl_regs[ kMode_idx ] = stack[0];
  424. // if repeat mode was enabled
  425. if( ctl_regs[ kMode_idx ] & kMode_Repeat_Fl )
  426. tmr0_reset();
  427. pwm1_init(); // the state of PWM may have been changed
  428. }
  429. break;
  430. case kWriteTable_Op:
  431. write_table();
  432. break;
  433. }
  434. }
  435. int main(void)
  436. {
  437. cli(); // mask all interupts
  438. DDRB |= _BV(ATTK_DIR) + _BV(HOLD_DIR) + _BV(LED_DIR); // setup PB4,PB3,PB1 as output
  439. PORTB &= ~(_BV(ATTK_PIN) + _BV(HOLD_PIN) + _BV(LED_PIN)); // clear output pins
  440. tmr0_init();
  441. pwm1_init();
  442. // setup i2c library
  443. usi_onReceiverPtr = on_receive;
  444. usi_onRequestPtr = on_request;
  445. usiTwiSlaveInit(I2C_SLAVE_ADDRESS);
  446. sei();
  447. PINB = _BV(LED_PIN); // writes to PINB toggle the pins
  448. _delay_ms(1000);
  449. PINB = _BV(LED_PIN); // writes to PINB toggle the pins
  450. // if in repeat mode
  451. if( ctl_regs[ kMode_idx ] & kMode_Repeat_Fl)
  452. tmr0_reset();
  453. while(1)
  454. {
  455. if (!usi_onReceiverPtr)
  456. {
  457. // no onReceive callback, nothing to do...
  458. continue;
  459. }
  460. if (!(USISR & ( 1 << USIPF )))
  461. {
  462. // Stop not detected
  463. continue;
  464. }
  465. uint8_t amount = usiTwiAmountDataInReceiveBuffer();
  466. if (amount == 0)
  467. {
  468. // no data in buffer
  469. continue;
  470. }
  471. usi_onReceiverPtr(amount);
  472. }
  473. return 0;
  474. }