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No commits in common. "d1c21fa48fd9e1b32e89bc69a2b5dff1f9c7220c" and "6b4c98869bc009b4b842d916da5275a60286de17" have entirely different histories.
d1c21fa48f
...
6b4c98869b
4
.gitignore
vendored
4
.gitignore
vendored
@ -1,4 +0,0 @@
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*.elf
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*.hex
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*.pyc
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_autosave*
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@ -1,7 +1,5 @@
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This is the main repository for the CML picadae hardware
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and a control files.
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- [__kicad__](kicad/README.md) contains the keyboard and pedal schematics and printed circuit board layout.
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- [__control__](control/README.md) contains the keyboard solenoid ATtiny85 firware, controller Arduino firmware and, Python control API and program.
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@ -17,8 +17,7 @@ class TinyOp(Enum):
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writeOp = 5
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writeTableOp = 6
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holdDelayOp = 7
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flagsOp = 8
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invalidOp = 9
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invalidOp = 8
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class TinyRegAddr(Enum):
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@ -41,22 +40,7 @@ class TinyRegAddr(Enum):
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kMaxAllowTmrAddr = 16
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kDelayCoarseAddr = 17
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kDelayFineAddr = 18
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kFlagsAddr = 19
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class TinyRegAddr0(Enum):
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kRdRegAddrAddr = 0
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kRdSrcAddr = 1
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kWrRegAddrAddr = 2
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kWrDstAddr = 3
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kAttkDutyAddr = 4
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kAttkDurHiAddr = 5
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kAttkDurLoAddr = 6
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kDecayStepAddr = 7
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kDecayDecrAddr = 8
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kPwmDutyAddr = 9
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kErrorCodeAddr = 10
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class TinyConst(Enum):
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kRdRegSrcId = TinyRegAddr.kRdRegAddrAddr.value # 0
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kRdTableSrcId = TinyRegAddr.kRdTableAddrAddr.value # 1
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@ -279,14 +263,6 @@ class Picadae:
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return res
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def set_flags( self, midi_pitch, flags ):
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return self.call_op( midi_pitch, TinyOp.flagsOp.value, [int(flags)] )
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#return self.call_op( midi_pitch, 5, [int(flags)] )
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def get_flags( self, midi_pitch, time_out_ms=250 ):
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return self.block_on_picadae_read_reg( midi_pitch, TinyRegAddr.kFlagsAddr.value, byteOutN=1, time_out_ms=time_out_ms )
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#return self.block_on_picadae_read_reg( midi_pitch, TinyRegAddr.kAttkDutyAddr.value, byteOutN=1, time_out_ms=time_out_ms )
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def set_velocity_map( self, midi_pitch, midi_vel, pulse_usec ):
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coarse,fine = self._usec_to_coarse_and_fine( pulse_usec )
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@ -345,18 +321,7 @@ class Picadae:
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self.make_note( midi_pitch, base_atk_us + i*delta_us, dur_ms )
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time.sleep( dur_ms / 1000.0 )
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return Result()
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def make_scale( self, pitch0, pitch1, atk_us, dur_ms ):
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if pitch0>pitch1:
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printf("pitch0 must be <= pitch1")
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else:
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for pitch in range(pitch0,pitch1+1):
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self.make_note( pitch, atk_us, dur_ms )
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time.sleep( dur_ms / 1000.0 )
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return Result()
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def set_log_level( self, log_level ):
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self.log_level = log_level
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return Result()
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@ -379,17 +344,6 @@ class Picadae:
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x = coarse*coarse_usec + fine*self.prescaler_usec
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#####
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# n = int(16e6*usec/(256*1e6))
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# coarse = n >> 8;
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# fine = n & 0xff;
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# x = usec
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####
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print("C:%i F:%i : %i %i (%i)" % (coarse,fine, x, usec, usec-x ))
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return coarse,fine
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@ -27,12 +27,9 @@ class PicadaeShell:
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'f':{ "func":"get_pwm_freq", "minN":1, "maxN":1, "help":"pwm freq <pitch>"},
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'I':{ "func":"set_pwm_div", "minN":2, "maxN":2, "help":"pwm div <pitch> <div> div:2=2,3=4,4=8,(5)=16 1us,6=32,7=64,8=128,9=256,10=512 32us, 11=1024,12=2048,13=4096,14=8192,15=16384"},
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'i':{ "func":"get_pwm_div", "minN":1, "maxN":1, "help":"pwm div <pitch>"},
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'A':{ "func":"set_flags", "minN":2, "maxN":2, "help":"set flags <pitch> <flags>"},
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'a':{ "func":"get_flags", "minN":1, "maxN":1, "help":"get flags <pitch>"},
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'W':{ "func":"write_table", "minN":1, "maxN":1, "help":"write_table <pitch>"},
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'N':{ "func":"make_note", "minN":3, "maxN":3, "help":"note <pitch> <atkUs> <durMs>"},
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'S':{ "func":"make_seq", "minN":5, "maxN":5, "help":"seq <pitch> <atkUs> <durMs> <deltaUs> <note_count>"},
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'C':{ "func":"make_scale", "minN":4, "maxN":4, "help":"scale <pitch0> <pitch1> <atkUs> <durMs>"},
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'S':{ "func":"make_seq", "minN":5, "maxN":5, "help":"seq <pitch> <atkUs> <durMs> <deltaUs> <note_count>"},
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'L':{ "func":"set_log_level", "minN":1, "maxN":1, "help":"log <level> (0-1)."}
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}
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@ -7,7 +7,7 @@ TTY=/dev/ttyACM0
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endif
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ifndef TARGET
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TARGET=i2c_timer_pwm_2
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TARGET=i2c_timer_pwm
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endif
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MCU=attiny85
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@ -1,685 +0,0 @@
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//| Copyright: (C) 2018-2020 Kevin Larke <contact AT larke DOT org>
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//| License: GNU GPL version 3.0 or above. See the accompanying LICENSE file.
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// w 60 0 1 10 : w i2c_addr SetPWM enable duty_val
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// w 60 5 12 8 32 : w i2c_addr write addrFl|src coarse_val
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// w 60 4 0 5 : w i2c_addr read src read_addr (set the read address to register 5)
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// r 60 4 3 : r i2c_addr <dum> cnt (read the first 3 reg's beginning w/ 5)
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/*
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AT TINY 85
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+--\/--+
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RESET _| 1 8 |_ +5V
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~OC1B HOLD PINB3 _| 2 7 |_ SCL yellow
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OC1B ONSET PINB4 _| 3 6 |_ PINB1 LED
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GND _| 4 5 |_ SDA orange
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+------+
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* = Serial and/or programming pins on Arduino as ISP
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*/
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// This program acts as the device (slave) for the control program i2c/a2a/c_ctl
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#define F_CPU 16000000L
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#include <stdio.h>
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#include <avr/io.h>
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#include <util/delay.h>
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#include <avr/interrupt.h>
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#include "usiTwiSlave.h"
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#define HOLD_DIR DDB3
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#define ATTK_DIR DDB4
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#define LED_DIR DDB1
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#define HOLD_PIN PINB3
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#define ATTK_PIN PINB4
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#define LED_PIN PINB1
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// Opcodes
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enum
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{
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kSetPwm_Op = 0, // Set PWM duty/hz/div 0 {<duty> {<freq> {<div>}}} div:2=2,3=4,4=8,5=16,6=32,7=64,8=128,9=256,10=512,11=1024,12=2048,13=4096,14=8192,15=16384
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kNoteOnVel_Op = 1, // Turn on note 3 {<vel>}
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kNoteOnUsec_Op = 2, // Turn on note 4 {<coarse> {<fine> {<prescale>}}}
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kNoteOff_Op = 3, // Turn off note 5
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kSetReadAddr_Op = 4, // Set a read addr. 6 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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kWrite_Op = 5, // Set write 7 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
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kWriteTable_Op = 6, // Write table to EEprom 9
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kHoldDelay_Op = 7, // Set hold delay {<coarse> {<fine>}}
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kFlags_Op = 8, // Set flags variable
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kInvalid_Op = 9 //
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};
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enum
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{
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kReg_Rd_Addr_idx = 0, // Next Reg Address to read
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kTable_Rd_Addr_idx = 1, // Next Table Address to read
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kEE_Rd_Addr_idx = 2, // Next EEPROM address to read
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kRead_Src_idx = 3, // kReg_Rd_Addr_idx=reg, kTable_Rd_Addr_idx=table, kEE_Rd_Addr_idx=eeprom
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kReg_Wr_Addr_idx = 4, // Next Reg Address to write
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kTable_Wr_Addr_idx = 5, // Next Table Address to write
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kEE_Wr_Addr_idx = 6, // Next EEPROM address to write
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kWrite_Dst_idx = 7, // kReg_Wr_Addr_idx=reg, kTable_Wr_Addr_idx=table, kEE_Wr_Addr_idx=eeprom
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kTmr_Coarse_idx = 8, //
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kTmr_Fine_idx = 9, //
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kTmr_Prescale_idx = 10, // Timer 0 clock divider: 1=1,2=8,3=64,4=256,5=1024 Default: 4 (16us)
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kPwm_Duty_idx = 11, //
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kPwm_Freq_idx = 12, //
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kPwm_Div_idx = 13, //
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kState_idx = 14, // 1=attk 2=hold
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kError_Code_idx = 15, // Error Code
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kMax_Coarse_Tmr_idx = 16, // Max. allowable coarse timer value
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kDelay_Coarse_idx = 17, // (17,18)=2000 (0,6)=100
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kDelay_Fine_idx = 18,
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kFlags_idx = 19,
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kMax_idx
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};
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enum
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{
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kState_Attk_Fl = 1,
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kState_Hold_Fl = 2
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};
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// ctl_regs[kFlags_idx] bits
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enum
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{
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kHoldOnAttk_Fl = 0x01
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};
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volatile uint8_t ctl_regs[] =
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{
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0, // 0 (0-(kMax_idx-1)) Reg Read Addr
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0, // 1 (0-255) Table Read Addr
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0, // 2 (0-255) EE Read Addr
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kReg_Rd_Addr_idx, // 3 (0-2) Read source
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0, // 4 (0-(kMax_idx-1)) Reg Write Addr
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0, // 5 (0-255) Table Write Addr
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0, // 6 (0-255) EE Write Addr
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kReg_Wr_Addr_idx, // 7 (0-2) Write source
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5, // 8 (0-255) Timer 0 Coarse Value (20400 us)
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0, // 9 (0-255) Timer 0 Fine Value
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4, // 10 (1-5) 4=16us per tick
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127, // 11 (0-255) Pwm Duty cycle
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255, // 12 (0-255) Pwm Frequency (123 Hz)
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5, // 13 (0-15) Pwm clock div
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0, // 14 state flags 1=attk 2=hold (read/only)
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0, // 15 (0-255) Error bit field
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14, // 16 (0-255) Max allowable coarse timer count
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0, // 17 (0-255) Hold coarse delay
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250, // 18 (0-255) Hold fine delay 0,6=100us 0,124=2000us w/ 16us Tmr0 tick
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0 // 19 (0-255) Flags 1=hold-on-attack
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};
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// These registers are saved to Eeprom
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uint8_t eeprom_addr[] =
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{
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kTmr_Prescale_idx,
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kPwm_Duty_idx,
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kPwm_Freq_idx,
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kPwm_Div_idx
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};
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#define tableN 256
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uint8_t table[ tableN ]; // [ coarse_0,fine_0, coarse_1, fine_1, .... coarse_127,fine_127]
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enum
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{
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kInvalid_Read_Src_ErrFl = 0x01,
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kInvalid_Write_Dst_ErrFl = 0x02,
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kInvalid_Coarse_Tmr_ErrFl = 0x04
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};
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#define set_error( flag ) ctl_regs[ kError_Code_idx ] |= (flag)
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//
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// EEPROM
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//
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void EEPROM_write(uint8_t ucAddress, uint8_t ucData)
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{
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// Wait for completion of previous write
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while(EECR & (1<<EEPE))
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{}
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EECR = (0<<EEPM1)|(0<<EEPM0); // Set Programming mode
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EEAR = ucAddress; // Set up address and data registers
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EEDR = ucData;
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EECR |= (1<<EEMPE); // Write logical one to EEMPE
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EECR |= (1<<EEPE); // Start eeprom write by setting EEPE
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}
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uint8_t EEPROM_read(uint8_t ucAddress)
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{
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// Wait for completion of previous write
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while(EECR & (1<<EEPE))
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{}
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EEAR = ucAddress; // Set up address register
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EECR |= (1<<EERE); // Start eeprom read by writing EERE
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return EEDR; // Return data from data register
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}
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void write_table()
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{
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uint8_t i;
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uint8_t regN = sizeof(eeprom_addr);
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// write the persistent registers
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for(i=0; i<regN; ++i)
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EEPROM_write( i, ctl_regs[ eeprom_addr[i] ] );
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// write the table
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for(i=0; i<tableN; ++i)
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EEPROM_write( regN+i, table[i] );
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}
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void load_table()
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{
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uint8_t i;
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uint8_t regN = sizeof(eeprom_addr);
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// read the persistent registers
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for(i=0; i<regN; ++i)
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ctl_regs[ eeprom_addr[i] ] = EEPROM_read(i);
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// read the tabke
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for(i=0; i<tableN; ++i)
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table[i] = EEPROM_read(regN + i);
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}
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//
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// Timer0
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//
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uint16_t stage1_cnt = 0;
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uint16_t stage2_cnt = 0;
|
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uint8_t stage1_coarse_cnt = 0;
|
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uint8_t stage1_fine_cnt = 0;
|
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uint8_t stage2_coarse_cnt = 0;
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uint8_t stage2_fine_cnt = 0;
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uint8_t hold_beg_first_fl = 0;
|
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volatile uint8_t tmr0_state = 0; // current timer mode: 0=disabled 1=coarse mode, 2=fine mode
|
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volatile uint8_t tmr0_coarse_cur = 0;
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||||
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||||
|
||||
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||||
#define set_attack() do { ctl_regs[kState_idx] |= kState_Attk_Fl; PORTB |= _BV(ATTK_PIN); } while(0)
|
||||
#define clear_attack() do { PORTB &= ~_BV(ATTK_PIN); ctl_regs[kState_idx] &= ~kState_Attk_Fl; } while(0)
|
||||
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#define clear_hold() PORTB &= ~(_BV(HOLD_PIN))
|
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#define set_hold() PORTB |= _BV(HOLD_PIN)
|
||||
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||||
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void hold_begin()
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{
|
||||
// Reset the PWM counter to to OCR1C (PWM TOP) so that it immediately triggers
|
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// set_hold() and latches any new value for OCR1B (See: 12.2.2 Timer/Counter1 in PWM Mode)
|
||||
// If this is not done and OCR1B was modified the first pulse will have the incorrect length.
|
||||
TCNT1 = ctl_regs[kPwm_Freq_idx];
|
||||
TIMSK |= _BV(OCIE1B) + _BV(TOIE1); // PWM interupt Enable interrupts
|
||||
|
||||
TCCR1 |= ctl_regs[ kPwm_Div_idx]; // 32us period (512 divider) prescaler
|
||||
GTCCR |= _BV(PSR1); // Force the pre-scale to be latched by setting PSR1
|
||||
|
||||
}
|
||||
|
||||
void hold_end()
|
||||
{
|
||||
clear_attack();
|
||||
clear_hold();
|
||||
TIMSK &= ~_BV(OCIE0A); // Clear timer interrupt (shouldn't be necessary but doesn't hurt on during note-off message)
|
||||
TIMSK &= ~(_BV(OCIE1B) + _BV(TOIE1)); // PWM interupt disable interrupts
|
||||
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||||
TCCR1 = 0; // Stop the PWM timer by setting the pre-scale to 0
|
||||
GTCCR |= _BV(PSR1); // Force the pre-scale to be latched by setting PSR1
|
||||
|
||||
}
|
||||
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||||
// Use the current tmr0 ctl_reg[] values to set the timer to the starting state.
|
||||
void tmr0_reset()
|
||||
{
|
||||
uint16_t delayCnt = ctl_regs[ kDelay_Coarse_idx ];
|
||||
delayCnt = (delayCnt<<8) + ctl_regs[ kDelay_Fine_idx ];
|
||||
|
||||
uint16_t attkCnt = ctl_regs[ kTmr_Coarse_idx ];
|
||||
attkCnt = (attkCnt<<8) + ctl_regs[ kTmr_Fine_idx ];
|
||||
|
||||
if( attkCnt > delayCnt )
|
||||
{
|
||||
stage1_cnt = attkCnt - delayCnt;
|
||||
stage2_cnt = delayCnt;
|
||||
hold_beg_first_fl = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
stage1_cnt = attkCnt;
|
||||
stage2_cnt = delayCnt - attkCnt;
|
||||
hold_beg_first_fl = 0;
|
||||
}
|
||||
|
||||
stage1_coarse_cnt = stage1_cnt >> 8;
|
||||
stage1_fine_cnt = stage1_cnt & 0xff;
|
||||
|
||||
stage2_coarse_cnt = stage2_cnt >> 8;
|
||||
stage2_fine_cnt = stage2_cnt & 0xff;
|
||||
|
||||
tmr0_coarse_cur = 0; // clear the coarse time counter
|
||||
|
||||
// always start in mode=1 because even if coarse count==0
|
||||
// because a COMPA interrupt will be fired immediately when the
|
||||
// timer starts
|
||||
tmr0_state = 1;
|
||||
OCR0A = 0xff;
|
||||
TCNT0 = 0;
|
||||
|
||||
clear_hold(); // clear the hold pin
|
||||
set_attack(); // set the attack pin
|
||||
|
||||
TIMSK |= _BV(OCIE0A); // enable the timer interrupt
|
||||
|
||||
//if( ctl_regs[ kFlags_idx ] & kHoldOnAttk_Fl )
|
||||
// hold_begin();
|
||||
|
||||
}
|
||||
|
||||
ISR(TIMER0_COMPA_vect)
|
||||
{
|
||||
switch( tmr0_state )
|
||||
{
|
||||
case 0: // timer disabled
|
||||
break;
|
||||
|
||||
case 1: // stage1 coarse mode
|
||||
// Note: the '+1' here is necessary to absorb an interrupt which is occurring
|
||||
// for an unknown reason. It must have something to do with resetting the
|
||||
// OCIE0A interrupt because it doesn't occur on the hold delay coarse timing.
|
||||
if( ++tmr0_coarse_cur >= stage1_coarse_cnt+1 )
|
||||
{
|
||||
tmr0_state = 2;
|
||||
OCR0A = stage1_fine_cnt;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: // stage1 fine mode complete
|
||||
|
||||
// if a coarse delay count exists then go into stage2 coarse mode
|
||||
if( stage2_coarse_cnt > 0 )
|
||||
{
|
||||
tmr0_state = 3;
|
||||
tmr0_coarse_cur = 0;
|
||||
OCR0A = 0xff;
|
||||
}
|
||||
else // otherwise go into fine mode
|
||||
{
|
||||
tmr0_state = 4;
|
||||
OCR0A = stage2_fine_cnt;
|
||||
}
|
||||
|
||||
if( hold_beg_first_fl )
|
||||
hold_begin(); // start hold PWM
|
||||
else
|
||||
clear_attack();
|
||||
|
||||
break;
|
||||
|
||||
case 3: // stage2 coarse mode
|
||||
if( ++tmr0_coarse_cur >= stage2_coarse_cnt )
|
||||
{
|
||||
tmr0_state = 4;
|
||||
OCR0A = stage2_fine_cnt;
|
||||
}
|
||||
break;
|
||||
|
||||
case 4: // stage2 fine mode complete
|
||||
TIMSK &= ~_BV(OCIE0A); // clear timer interrupt
|
||||
tmr0_state = 0;
|
||||
|
||||
if( hold_beg_first_fl )
|
||||
clear_attack();
|
||||
else
|
||||
hold_begin();
|
||||
|
||||
//if( !(ctl_regs[ kFlags_idx ] & kHoldOnAttk_Fl) )
|
||||
// hold_begin();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
void tmr0_init()
|
||||
{
|
||||
TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
|
||||
TCCR0A = 0; // Set the timer control registers to their default value
|
||||
TCCR0B = 0;
|
||||
TCCR0A |= 0x02; // CTC mode
|
||||
TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
|
||||
GTCCR |= _BV(PSR0); // Trigger the pre-scaler to be reset to the selected value
|
||||
}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Pwm
|
||||
//
|
||||
// PWM is optimized to use pins OC1A ,~OC1A, OC1B, ~OC1B
|
||||
// but since these pins are not available this code uses
|
||||
// ISR's to redirect the output to PIN3
|
||||
|
||||
void pwm1_update()
|
||||
{
|
||||
OCR1B = ctl_regs[kPwm_Duty_idx]; // control duty cycle
|
||||
OCR1C = ctl_regs[kPwm_Freq_idx]; // PWM frequency pre-scaler
|
||||
}
|
||||
|
||||
|
||||
// Called when TCNT1 == OCR1C.
|
||||
// At this point TCNT1 is reset to 0, new OCR1B values are latched from temp. loctaion to OCR1B
|
||||
ISR(TIMER1_OVF_vect)
|
||||
{
|
||||
set_hold();
|
||||
}
|
||||
|
||||
// Called when TCNT1 == OCR1B
|
||||
ISR(TIMER1_COMPB_vect)
|
||||
{
|
||||
clear_hold();
|
||||
}
|
||||
|
||||
|
||||
void pwm1_init()
|
||||
{
|
||||
DDRB |= _BV(HOLD_DIR); // setup PB3 as output
|
||||
|
||||
TCCR1 = 0; // Set the control registers to their default
|
||||
GTCCR = 0;
|
||||
GTCCR |= _BV(PWM1B); // Enable PWM B and disconnect output pins
|
||||
|
||||
pwm1_update();
|
||||
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Tracks the current register pointer position
|
||||
volatile uint8_t reg_position = 0;
|
||||
const uint8_t reg_size = sizeof(ctl_regs);
|
||||
|
||||
//
|
||||
// Read Request Handler
|
||||
//
|
||||
// This is called for each read request we receive, never put more
|
||||
// than one byte of data (with TinyWireS.send) to the send-buffer when
|
||||
// using this callback
|
||||
//
|
||||
|
||||
void on_request()
|
||||
{
|
||||
uint8_t val = 0;
|
||||
|
||||
switch( ctl_regs[ kRead_Src_idx ] )
|
||||
{
|
||||
case kReg_Rd_Addr_idx:
|
||||
val = ctl_regs[ ctl_regs[kReg_Rd_Addr_idx] ];
|
||||
break;
|
||||
|
||||
case kTable_Rd_Addr_idx:
|
||||
val = table[ ctl_regs[kTable_Rd_Addr_idx] ];
|
||||
break;
|
||||
|
||||
case kEE_Rd_Addr_idx:
|
||||
val = EEPROM_read(ctl_regs[kEE_Rd_Addr_idx]);
|
||||
break;
|
||||
|
||||
default:
|
||||
set_error( kInvalid_Read_Src_ErrFl );
|
||||
return;
|
||||
}
|
||||
|
||||
usiTwiTransmitByte(val);
|
||||
|
||||
ctl_regs[ ctl_regs[ kRead_Src_idx ] ] += 1;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void _write_op( uint8_t* stack, uint8_t stackN )
|
||||
{
|
||||
uint8_t stack_idx = 0;
|
||||
|
||||
if( stackN > 0 )
|
||||
{
|
||||
uint8_t src = stack[0] & 0x07;
|
||||
uint8_t addr_fl = stack[0] & 0x08;
|
||||
|
||||
// verify the source value
|
||||
if( src < kReg_Wr_Addr_idx || src > kEE_Wr_Addr_idx )
|
||||
{
|
||||
set_error( kInvalid_Write_Dst_ErrFl );
|
||||
return;
|
||||
}
|
||||
|
||||
// set the write source
|
||||
stack_idx = 1;
|
||||
ctl_regs[ kWrite_Dst_idx ] = src;
|
||||
|
||||
// if an address value was passed also ....
|
||||
if( addr_fl && stackN > 1 )
|
||||
{
|
||||
stack_idx = 2;
|
||||
ctl_regs[ src ] = stack[1];
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
for(; stack_idx<stackN; ++stack_idx)
|
||||
{
|
||||
uint8_t addr_idx = ctl_regs[ ctl_regs[kWrite_Dst_idx] ]++;
|
||||
uint8_t val = stack[ stack_idx ];
|
||||
|
||||
switch( ctl_regs[ kWrite_Dst_idx ] )
|
||||
{
|
||||
case kReg_Wr_Addr_idx: ctl_regs[ addr_idx ] = val; break;
|
||||
case kTable_Wr_Addr_idx: table[ addr_idx ] = val; break;
|
||||
case kEE_Wr_Addr_idx: EEPROM_write( table[ addr_idx ], val); break;
|
||||
|
||||
default:
|
||||
set_error( kInvalid_Write_Dst_ErrFl );
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// The I2C data received -handler
|
||||
//
|
||||
// This needs to complete before the next incoming transaction (start,
|
||||
// data, restart/stop) on the bus does so be quick, set flags for long
|
||||
// running tasks to be called from the mainloop instead of running
|
||||
// them directly,
|
||||
//
|
||||
|
||||
void on_receive( uint8_t byteN )
|
||||
{
|
||||
PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
||||
|
||||
const uint8_t stackN = 16;
|
||||
uint8_t stack_idx = 0;
|
||||
uint8_t stack[ stackN ];
|
||||
uint8_t i;
|
||||
|
||||
if (byteN < 1 || byteN > TWI_RX_BUFFER_SIZE)
|
||||
{
|
||||
// Sanity-check
|
||||
return;
|
||||
}
|
||||
|
||||
// get the register index to read/write
|
||||
uint8_t op_id = usiTwiReceiveByte();
|
||||
|
||||
byteN--;
|
||||
|
||||
// If only one byte was received then this was a read request
|
||||
// and the buffer pointer (reg_position) is now set to return the byte
|
||||
// at this location on the subsequent call to on_request() ...
|
||||
if(byteN)
|
||||
{
|
||||
while( byteN-- )
|
||||
{
|
||||
stack[stack_idx] = usiTwiReceiveByte();
|
||||
++stack_idx;
|
||||
}
|
||||
}
|
||||
|
||||
switch( op_id )
|
||||
{
|
||||
case kSetPwm_Op:
|
||||
for(i=0; i<stack_idx && i<3; ++i)
|
||||
ctl_regs[ kPwm_Duty_idx + i ] = stack[i];
|
||||
|
||||
pwm1_update();
|
||||
break;
|
||||
|
||||
|
||||
case kNoteOnUsec_Op:
|
||||
for(i=0; i<stack_idx && i<3; ++i)
|
||||
ctl_regs[ kTmr_Coarse_idx + i ] = stack[i];
|
||||
|
||||
// validate the coarse error value
|
||||
if( ctl_regs[ kTmr_Coarse_idx ] > ctl_regs[ kMax_Coarse_Tmr_idx ])
|
||||
{
|
||||
ctl_regs[ kTmr_Coarse_idx ] = ctl_regs[ kMax_Coarse_Tmr_idx ];
|
||||
set_error( kInvalid_Coarse_Tmr_ErrFl );
|
||||
}
|
||||
// if a prescaler was included then the timer needs to be re-initialized
|
||||
if( i == 3 )
|
||||
{
|
||||
cli();
|
||||
tmr0_init();
|
||||
sei();
|
||||
}
|
||||
|
||||
tmr0_reset();
|
||||
break;
|
||||
|
||||
case kNoteOff_Op:
|
||||
hold_end();
|
||||
break;
|
||||
|
||||
case kSetReadAddr_Op:
|
||||
if( stack_idx > 0 )
|
||||
{
|
||||
ctl_regs[ kRead_Src_idx ] = stack[0];
|
||||
|
||||
if( stack_idx > 1 )
|
||||
ctl_regs[ ctl_regs[ kRead_Src_idx ] ] = stack[1];
|
||||
}
|
||||
break;
|
||||
|
||||
case kWrite_Op:
|
||||
_write_op( stack, stack_idx );
|
||||
break;
|
||||
|
||||
case kWriteTable_Op:
|
||||
write_table();
|
||||
break;
|
||||
|
||||
case kHoldDelay_Op:
|
||||
for(i=0; i<stack_idx && i<2; ++i)
|
||||
ctl_regs[ kDelay_Coarse_idx + i ] = stack[i];
|
||||
|
||||
break;
|
||||
|
||||
case kFlags_Op:
|
||||
ctl_regs[ kFlags_idx ] = stack[0];
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
cli(); // mask all interupts
|
||||
|
||||
DDRB |= _BV(ATTK_DIR) + _BV(HOLD_DIR) + _BV(LED_DIR); // setup PB4,PB3,PB1 as output
|
||||
PORTB &= ~(_BV(ATTK_PIN) + _BV(HOLD_PIN) + _BV(LED_PIN)); // clear output pins
|
||||
|
||||
tmr0_init();
|
||||
pwm1_init();
|
||||
|
||||
// setup i2c library
|
||||
usi_onReceiverPtr = on_receive;
|
||||
usi_onRequestPtr = on_request;
|
||||
usiTwiSlaveInit(I2C_SLAVE_ADDRESS);
|
||||
|
||||
sei();
|
||||
|
||||
PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
||||
_delay_ms(1000);
|
||||
PINB = _BV(LED_PIN); // writes to PINB toggle the pins
|
||||
|
||||
|
||||
while(1)
|
||||
{
|
||||
|
||||
if (!usi_onReceiverPtr)
|
||||
{
|
||||
// no onReceive callback, nothing to do...
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(USISR & ( 1 << USIPF )))
|
||||
{
|
||||
// Stop not detected
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
uint8_t amount = usiTwiAmountDataInReceiveBuffer();
|
||||
if (amount == 0)
|
||||
{
|
||||
// no data in buffer
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
usi_onReceiverPtr(amount);
|
||||
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -40,16 +40,13 @@ Change Activity:
|
||||
/********************************************************************************
|
||||
includes
|
||||
********************************************************************************/
|
||||
#include <stddef.h>
|
||||
|
||||
#include <avr/io.h>
|
||||
#include <avr/interrupt.h>
|
||||
|
||||
#include "usiTwiSlave.h"
|
||||
//#include "../common/util.h"
|
||||
|
||||
//request_func_t _onTwiDataRequest = NULL;
|
||||
request_func_t usi_onRequestPtr = NULL;
|
||||
receive_func_t usi_onReceiverPtr = NULL;
|
||||
|
||||
/********************************************************************************
|
||||
device dependent defines
|
||||
|
||||
@ -36,7 +36,6 @@ Change Activity:
|
||||
|
||||
|
||||
|
||||
|
||||
/********************************************************************************
|
||||
|
||||
includes
|
||||
@ -53,26 +52,17 @@ Change Activity:
|
||||
|
||||
********************************************************************************/
|
||||
|
||||
|
||||
void usiTwiSlaveInit( uint8_t );
|
||||
void usiTwiTransmitByte( uint8_t );
|
||||
uint8_t usiTwiReceiveByte( void );
|
||||
bool usiTwiDataInReceiveBuffer( void );
|
||||
//void (*_onTwiDataRequest)(void);
|
||||
|
||||
//extern request_func_t _onTwiDataRequest;
|
||||
|
||||
void (*_onTwiDataRequest)(void);
|
||||
bool usiTwiDataInTransmitBuffer(void);
|
||||
uint8_t usiTwiAmountDataInReceiveBuffer(void);
|
||||
// on_XXX handler pointers
|
||||
//void (*usi_onRequestPtr)(void);
|
||||
//void (*usi_onReceiverPtr)(uint8_t);
|
||||
void (*usi_onRequestPtr)(void);
|
||||
void (*usi_onReceiverPtr)(uint8_t);
|
||||
|
||||
typedef void (*request_func_t)(void);
|
||||
typedef void (*receive_func_t)(uint8_t);
|
||||
|
||||
extern request_func_t usi_onRequestPtr;
|
||||
extern receive_func_t usi_onReceiverPtr;
|
||||
|
||||
/********************************************************************************
|
||||
|
||||
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 381 KiB |
Loading…
Reference in New Issue
Block a user