ctrl/main.c, tiny/i2c_timer_pwm.c : Updated comments.
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@ -218,11 +218,10 @@ int main (void)
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else
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{
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// TODO: handle case where there are no data bytes (only e.g. note-off)
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state = kWait_for_value;
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data_buf[0] = dev_reg_addr; // make 'dev_reg_addr' the first data value to write
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data_buf_idx = 1; //
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op_byte_cnt += 1; // incr op_byte_cnt to account for 'dev_reg_addr' as first byte
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state = kWait_for_value;
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data_buf[0] = dev_reg_addr; // make 'dev_reg_addr' the first data value to write
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data_buf_idx = 1; //
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op_byte_cnt += 1; // incr op_byte_cnt to account for 'dev_reg_addr' as first byte
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}
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break;
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@ -42,7 +42,6 @@ enum
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kSetReadAddr_Op = 4, // Set a read addr. 4 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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kWrite_Op = 5, // Set write 5 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
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kSetMode_Op = 6, // Set the mode flags 6 {<mode>} 1=repeat 2=pwm
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kInvalid_Op = 7 //
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};
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@ -94,15 +93,19 @@ volatile uint8_t ctl_regs[] =
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0, // 1 (0-255) Table Read Addr
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0, // 2 (0-255) EE Read Addr
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kReg_Rd_Addr_idx, // 3 (0-2) Read source
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0, // 4 (0-(kMax_idx-1)) Reg Write Addr
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0, // 5 (0-255) Table Write Addr
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0, // 6 (0-255) EE Write Addr
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kReg_Wr_Addr_idx, // 7 (0-2) Write source
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245, // 8 (0-255) Timer 0 Coarse Value
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25, // 9 (0-255) Timer 0 Fine Value
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4, // 10 (1-5) 4=16us per tick
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127, // 11 (0-255) Pwm Duty cycle
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254, // 12 (0-255) Pwm Frequency (123 hz)
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254, // 12 (0-255) Pwm Frequency (123 Hz)
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kMode_Repeat_Fl, // 13 mode flags 1=Repeat 2=PWM
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0, // 14 state flags 1=attk 2=hold
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0, // 15 (0-255) Error bit field
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@ -295,11 +298,10 @@ ISR(TIMER0_COMPA_vect)
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void tmr0_init()
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{
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TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
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TCCR0A |= 0x02; // CTC mode
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TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
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TCCR0A |= 0x02; // CTC mode
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TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
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GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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}
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