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ctrl/main.c, tiny/i2c_timer_pwm.c : Updated comments.

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This commit is contained in:
kevin.larke 2019-08-07 21:52:23 -04:00
parent 3e00b5110d
commit f24aec16e6
2 changed files with 14 additions and 13 deletions
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9
control/ctrl/main.c
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@ -218,11 +218,10 @@ int main (void)
else else
{ {
// TODO: handle case where there are no data bytes (only e.g. note-off) // TODO: handle case where there are no data bytes (only e.g. note-off)
state = kWait_for_value; state = kWait_for_value;
data_buf[0] = dev_reg_addr; // make 'dev_reg_addr' the first data value to write data_buf[0] = dev_reg_addr; // make 'dev_reg_addr' the first data value to write
data_buf_idx = 1; // data_buf_idx = 1; //
op_byte_cnt += 1; // incr op_byte_cnt to account for 'dev_reg_addr' as first byte op_byte_cnt += 1; // incr op_byte_cnt to account for 'dev_reg_addr' as first byte
} }
break; break;

14
control/tiny/i2c_timer_pwm.c
View File

@ -42,7 +42,6 @@ enum
kSetReadAddr_Op = 4, // Set a read addr. 4 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom kSetReadAddr_Op = 4, // Set a read addr. 4 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
kWrite_Op = 5, // Set write 5 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom kWrite_Op = 5, // Set write 5 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
kSetMode_Op = 6, // Set the mode flags 6 {<mode>} 1=repeat 2=pwm kSetMode_Op = 6, // Set the mode flags 6 {<mode>} 1=repeat 2=pwm
kInvalid_Op = 7 // kInvalid_Op = 7 //
}; };
@ -94,15 +93,19 @@ volatile uint8_t ctl_regs[] =
0, // 1 (0-255) Table Read Addr 0, // 1 (0-255) Table Read Addr
0, // 2 (0-255) EE Read Addr 0, // 2 (0-255) EE Read Addr
kReg_Rd_Addr_idx, // 3 (0-2) Read source kReg_Rd_Addr_idx, // 3 (0-2) Read source
0, // 4 (0-(kMax_idx-1)) Reg Write Addr 0, // 4 (0-(kMax_idx-1)) Reg Write Addr
0, // 5 (0-255) Table Write Addr 0, // 5 (0-255) Table Write Addr
0, // 6 (0-255) EE Write Addr 0, // 6 (0-255) EE Write Addr
kReg_Wr_Addr_idx, // 7 (0-2) Write source kReg_Wr_Addr_idx, // 7 (0-2) Write source
245, // 8 (0-255) Timer 0 Coarse Value 245, // 8 (0-255) Timer 0 Coarse Value
25, // 9 (0-255) Timer 0 Fine Value 25, // 9 (0-255) Timer 0 Fine Value
4, // 10 (1-5) 4=16us per tick 4, // 10 (1-5) 4=16us per tick
127, // 11 (0-255) Pwm Duty cycle 127, // 11 (0-255) Pwm Duty cycle
254, // 12 (0-255) Pwm Frequency (123 hz) 254, // 12 (0-255) Pwm Frequency (123 Hz)
kMode_Repeat_Fl, // 13 mode flags 1=Repeat 2=PWM kMode_Repeat_Fl, // 13 mode flags 1=Repeat 2=PWM
0, // 14 state flags 1=attk 2=hold 0, // 14 state flags 1=attk 2=hold
0, // 15 (0-255) Error bit field 0, // 15 (0-255) Error bit field
@ -295,11 +298,10 @@ ISR(TIMER0_COMPA_vect)
void tmr0_init() void tmr0_init()
{ {
TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
TCCR0A |= 0x02; // CTC mode TCCR0A |= 0x02; // CTC mode
TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
} }