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@@ -42,7 +42,6 @@ enum
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42
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42
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kSetReadAddr_Op = 4, // Set a read addr. 4 {<src>} {<addr>} } src: 0=reg 1=table 2=eeprom
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43
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43
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kWrite_Op = 5, // Set write 5 {<addrfl|src> {addr} {<value0> ... {<valueN>}} addrFl:0x80 src: 4=reg 5=table 6=eeprom
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44
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44
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kSetMode_Op = 6, // Set the mode flags 6 {<mode>} 1=repeat 2=pwm
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45
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-
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46
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45
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kInvalid_Op = 7 //
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47
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46
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};
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48
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47
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@@ -93,16 +92,20 @@ volatile uint8_t ctl_regs[] =
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93
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92
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0, // 0 (0-(kMax_idx-1)) Reg Read Addr
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94
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93
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0, // 1 (0-255) Table Read Addr
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95
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94
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0, // 2 (0-255) EE Read Addr
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96
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- kReg_Rd_Addr_idx, // 3 (0-2) Read source
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95
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+ kReg_Rd_Addr_idx, // 3 (0-2) Read source
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96
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+
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97
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97
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0, // 4 (0-(kMax_idx-1)) Reg Write Addr
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98
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98
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0, // 5 (0-255) Table Write Addr
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99
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- 0, // 6 (0-255) EE Write Addr
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99
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+ 0, // 6 (0-255) EE Write Addr
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100
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100
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kReg_Wr_Addr_idx, // 7 (0-2) Write source
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101
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+
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101
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102
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245, // 8 (0-255) Timer 0 Coarse Value
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102
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103
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25, // 9 (0-255) Timer 0 Fine Value
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103
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104
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4, // 10 (1-5) 4=16us per tick
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105
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+
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104
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106
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127, // 11 (0-255) Pwm Duty cycle
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105
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- 254, // 12 (0-255) Pwm Frequency (123 hz)
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107
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+ 254, // 12 (0-255) Pwm Frequency (123 Hz)
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108
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+
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106
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109
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kMode_Repeat_Fl, // 13 mode flags 1=Repeat 2=PWM
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107
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110
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0, // 14 state flags 1=attk 2=hold
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108
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111
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0, // 15 (0-255) Error bit field
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@@ -295,11 +298,10 @@ ISR(TIMER0_COMPA_vect)
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298
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296
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299
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void tmr0_init()
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297
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300
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{
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298
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- TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
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299
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- TCCR0A |= 0x02; // CTC mode
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301
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+ TIMSK &= ~_BV(OCIE0A); // Disable interrupt TIMER1_OVF
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302
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+ TCCR0A |= 0x02; // CTC mode
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300
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303
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TCCR0B |= ctl_regs[kTmr_Prescale_idx]; // set the prescaler
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301
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-
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302
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- GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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304
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+ GTCCR |= _BV(PSR0); // Set the pre-scaler to the selected value
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303
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305
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}
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304
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306
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305
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307
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