43 lines
860 B
Prolog
43 lines
860 B
Prolog
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update=Wed 21 Oct 2020 02:51:13 PM EDT
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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[eeschema]
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version=1
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LibDir=
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